SE98 Datasheet, PDF (11/39 Pages) NXP Semiconductors – DDR memory module temp sensor, 3.3 V

NXP Semiconductors
SE98
DDR memory module temp sensor, 3.3 V
Table 4.
Register
01h
Registers to be initialized
Default value Example value
0000h
0209h
02h
0000h
03h
0000h
04h
0000h
22h
0000h
0550h
1F40h
05F0h
0000h
Description
Configuration register
• hysteresis = 1.5 °C
• EVENT output = Interrupt mode
• EVENT output is enabled
Upper Boundary Alarm Trip register = 85 °C
Lower Boundary Alarm Trip register = −20 °C
Critical Alarm Trip register = 95 °C
SMBus register = no change
7.7 SMBus time-out
The SE98 supports the SMBus time-out feature. If the host holds SCL LOW between
25 ms and 35 ms, the SE98 would reset its internal state machine to the bus idle state to
prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out
is disabled by writing a logic 1 to bit 7 of register 22h.
Remark: When SMBus time-out is enabled, the I²C-bus minimum bus speed is limited by
the SMBus time-out timer, and goes down to only 10 kHz.
7.8 SMBus Alert
The SE98 supports SMBus Alert when it is programmed for the Interrupt mode and when
the EVENT polarity bit is set to logic 0. The EVENT pin can be ANDed with other EVENT
or ALERT signals from other slave devices to signal their intention to communicate with
the host controller. When the host detects EVENT or ALERT signal LOW, it issues an
Alert Response Address (ARA) to which a slave device would respond with its address.
When there are multiple slave devices generating an Alert the SE98 performs bus
arbitration. If it wins the bus, it responds to the ARA and then clears the EVENT pin.
Remark: Either in comparator mode or when the SE98 crosses the critical temperature,
the host must also read the EVENT status bit and provide remedy to the situation by
bringing the temperature to within the alarm window or below the critical temperature if
that bit is set. Otherwise, the EVENT pin will not get de-asserted.
START bit
read
Alert Response Address
acknowledge
not acknowledge STOP bit
device address
S 0 0 0 1 1 0 0 1 0 0 0 1 1 A2 A1 A0 0 1 P
host detects
SMBus ALERT
master sends a START bit,
ARA and a read command
Slave acknowledges and
sends its slave address.
The last bit of slave address
is hard coded '0'.
host NACK and
sends a STOP bit
002aab330
Fig 6. How SE98 responds to SMBus Alert
SE98_4
Product data sheet
Rev. 04 — 2 February 2009
© NXP B.V. 2009. All rights reserved.
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