SE98 Datasheet, PDF (24/39 Pages) NXP Semiconductors – DDR memory module temp sensor, 3.3 V

NXP Semiconductors
SE98
DDR memory module temp sensor, 3.3 V
8.8 Device ID register
The device ID and device revision are A1h and 00h, respectively.
Table 21. Device ID register bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Device ID
Reset
1
0
1
0
0
0
0
1
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
Device revision
Reset
0
0
0
0
0
0
0
1
Access
R
R
R
R
R
R
R
R
8.9 SMBus register
Table 22. SMBus Time-out register bit allocation
Bit
15
14
13
12
11
10
Symbol
RFU
Reset
0
0
0
0
0
0
Access
R
R
R
R
R
R
Bit
7
6
5
4
3
2
Symbol STMOUT
RFU
Reset
0
0
0
0
0
0
Access
R/W
R
R
R
R
R
9
8
0
0
R
R
1
0
SALRT
0
0
R
R/W
Table 23. SMBus Time-out register bit description
Bit
Symbol Description
15:8
RFU
reserved; always 0
7
STMOUT SMBus time-out.
0 — SMBus time-out is enabled (default)
1 — disable SMBus time-out
When either of the lock bits is set, this bit cannot be altered until unlocked.
6:1
RFU
reserved; always 0
0
SALRT
SMBus Alert.
0 — SMBus Alert is enabled (default)
1 — disable SMBus Alert
When either of the lock bits is set, this bit cannot be altered until unlocked.
SE98_4
Product data sheet
Rev. 04 — 2 February 2009
© NXP B.V. 2009. All rights reserved.
24 of 39