DS90UR905Q Datasheet, PDF (9/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Pin Name
Pin #
NC
1, 15, 16,
30, 31, 45,
46, 60
FPD-Link II Serial Interface
RIN+
49
RIN-
50
CMF
51
I/O, Type
I, LVDS
I, LVDS
I, Analog
CMLOUTP
52
O, LVDS
CMLOUTN
53
O, LVDS
Power and Ground
VDDL
29
VDDIR
48
VDDR
43, 55
VDDSC
4, 58
VDDPR
57
VDDCMLO
54
VDDIO
13, 24, 38
GND
DAP
Power
Power
Power
Power
Power
Power
Power
Ground
Description
Not Connected
Leave pin open (float)
True Input. The input must be AC Coupled with a 100 nF capacitor.
Inverting Input. The input must be AC Coupled with a 100 nF capacitor.
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Logic Power, 1.8 V ±5%
Input Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V_DDIO)
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connected to the ground plane (GND) with at least 9 vias.
NOTE: 1 = HIGH, 0 = LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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