DS90UR905Q Datasheet, PDF (5/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Pin Name
Pin #
I/O, Type Description
BISTEN
31
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[2:0]
18, 16, 15 I, LVCMOS Reserved - tie LOW
w/ pull-down
FPD-Link II Serial Interface
DOUT+
20
O, LVDS True Output.
The output must be AC Coupled with a 100 nF capacitor.
DOUT-
19
O, LVDS Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
Power and Ground
VDDL
7
Power Logic Power, 1.8 V ±5%
VDDP
14
Power PLL Power, 1.8 V ±5%
VDDHS
17
Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX
22
Power Output Driver Power, 1.8 V ±5%
VDDIO
30
Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
NOTE: 1= HIGH, 0 L= LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
5
www.national.com