DS90UR905Q Datasheet, PDF (25/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

SERIALIZER FUNCTIONAL DESCRIPTION
The Ser converts a wide parallel input bus to a single serial
output data stream, and also acts as a signal generator for
the chipset Built In Self Test (BIST) mode. The device can be
configured via external pins or through the optional serial
control bus. The Ser features enhance signal quality on the
link by supporting: a selectable VOD level, a selectable de-
emphasis signal conditioning and also the FPD-Link II data
coding that provides randomization, scrambling, and DC Bal-
anacing of the video data. The Ser includes multiple features
to reduce EMI associated with display data transmission. This
includes the randomization and scrambling of the data and
also the system spread spectrum PCLK support. The Ser
features power saving features with a sleep mode, auto stop
clock feature, and optional LVCMOS (1.8 V) parallel bus com-
patibility.
See also the Functional Description of the chipset's serial
control bus and BIST modes.
EMI Reduction Features
Data Randomization & Scrambling
Text to come.
Ser — Spread Spectrum Compatibility
The Ser PCLK is capable of tracking spread spectrum clock-
ing (SSC) from a host source. The PCLK will accept spread
spectrum tracking up to 35kHz modulation and ±0.5, ±1 or
±2% deviations (center spread). The maximum conditions for
the PCLK input are: a modulation frequency of 35kHz and
amplitude deviations of ±2% (4% total).
Signal Quality Enhancers
Ser — VOD Select (VODSEL)
The Ser differential output voltage may be increased by set-
ting the VODSEL pin High. When VODSEL is Low, the VOD
is at the standard (default) level. When VODSEL is High, the
DC VOD is increased in level. The increased VOD is useful
in extremely high noise environments and also on extra long
cable length applications. When using de-emphasis it is rec-
ommended to set VODSEL = H to avoid excessive signal
attenuation especially with the larger de-emphasis settings.
This feature may be controlled by the external pin or by reg-
ister.
TABLE 3. Differential Output Voltage
Input
Effect
VODSEL
VOD
mV
VOD
mVp-p
H
±420
840
L
±280
560
Ser — De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis be-
ginning one full bit time after a logic transition that the Ser
drives. This is useful to counteract loading effects of long or
lossy cables. This pin should be left open for standard switch-
ing currents (no de-emphasis) or if controlled by register. De-
emphasis is selected by connecting a resistor on this pin to
ground, with R value between 0.5 kΩ to 1 MΩ, or by register
setting. When using De-Emphasis it is recommended to set
VODSEL = H.
TABLE 4. De-Emphasis Resistor Value
Resistor Value (kΩ)
Open
De-Emphasis Setting
Disabled
0.6
- 12 dB
1.0
- 9 dB
2.0
- 6 dB
5.0
- 3 dB
30102060
FIGURE 21. De-Emph vs. R value
Power Saving Features
Ser — Power Down Feature (PDB)
The Ser has a PDB input pin to ENABLE or POWER DOWN
the device. This pin is controlled by the host and is used to
save power, disabling the link when the display is not needed.
In the POWER DOWN mode, the high-speed driver outputs
are both pulled to VDD and present a 0V VOD state. Note –
in POWER DOWN, the optional Serial Bus Control Registers
are RESET.
Ser — Stop Clock Feature
The Ser will enter a low power SLEEP state when the PCLK
is stopped. A STOP condition is detected when the input clock
frequency is less than 3 MHz. The clock should be held at a
static Low or high state. When the PCLK starts again, the Ser
will then lock to the valid input PCLK and then transmits the
RGB data to the Des. Note – in STOP CLOCK SLEEP, the
optional Serial Bus Control Registers values are RE-
TAINED.
1.8V or 3.3V VDDIO Operation
The Ser parallel bus and Serial Bus Interface can operate with
1.8 V or 3.3 V levels (V_DDIO) for host compatibility. The 1.8 V
levels will offer lower noise (EMI) and also a system power
savings.
Ser — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on.
If RFB is High, input data is latched on the Rising edge of the
PCLK. If RFB is Low, input data is latched on the Falling edge
of the PCLK. Ser and Des maybe set differently. This feature
may be controlled by the external pin or by register.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus
Control Interface.
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