DS90UR905Q Datasheet, PDF (8/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Pin Name
Pin #
I/O, Type Description
OS_PCLK
11 [B5]
STRAP PCLK Output Slew Select — Pin or Register Control
I, LVCMOS OS_PCLK = 1, increased PCLK slew
w/ pull-down OS_PCLK = 0, normal (default)
OS_DATA
14 [B3]
STRAP Data Output Slew Select — Pin or Register Control
I, LVCMOS OS_DATA = 1, increased DATA slew
w/ pull-down OS_DATA = 0, normal (default)
OP_LOW
42 PASS
STRAP Outputs held Low when LOCK = 1 — Pin or Register Control
I, LVCMOS NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS
w/ pull-down STRAP FUNCTION
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH
NOTE: Before the device is powered up, the outputs are in tri-state.
See Figure 26 and Figure 27.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
OSS_SEL
17 [B2]
STRAP Output Sleep State Select — Pin or Register Control
I, LVCMOS NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW =1
w/ pull-down OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See Table 8).
RFB
18 [B1]
STRAP Pixel Clock Output Strobe Edge Select — Pin or Register Control
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
EQ[3:0]
20 [G7],
21 [G6],
22 [G5],
23 [G4]
STRAP Receiver Input Equalization — Pin or Register Control
I, LVCMOS (See Table 5).
w/ pull-down
OSC_SEL[2:0]
26 [G2],
27 [G1],
28 [G0]
STRAP Oscillator Select — Pin or Register Control
I, LVCMOS (See Table 9 and Table 10).
w/ pull-down
SSC[3:0]
34 [R6],
35 [R5],
36 [R4],
37 R[3]
STRAP Spread Spectrum Clock Generation (SSCG) Range Select — Pin or Register Control
I, LVCMOS (See Table 6 and Table 7).
w/ pull-down
MAP_SEL[1:0]
40 [R1],
41 [R0]
STRAP Bit Mapping Backward Compatibility / DS90UR241 Options — Pin or Register Control
I, LVCMOS Normal setting to b'00. See (Table 11).
w/ pull-down
Control and Configuration
PDB
59
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by Table
8. Control Registers are RESET.
ID[x]
56
I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 12).
SCL
SDA
3
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
2
I/O,
Serial Control Bus Data Input / Output - Optional
LVCMOS SDA requires an external pull-up resistor to V_DDIO.
Open Drain
BISTEN
44
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES
47
I, LVCMOS Reserved - tie LOW
w/ pull-down
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