DS90UR905Q Datasheet, PDF (13/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Symbol
Parameter
Conditions
Pin/Freq.
LVDS RECEIVER DC SPECIFICATIONS
V_TH
Differential Input Threshold
High Voltage
V_TL
Differential Input Threshold
Low Voltage
V_CM = +1.2V (Internal V_BIAS)
Common Mode Voltage,
V_CM
Internal V_BIAS
I_IN
Input Current
V_IN = 0V or V_DDIO
R_T
Internal Termination Resistor
CMLOUTP/N DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
RIN+, RIN-
RIN+, RIN-
V_OD
Differential Output Voltage
R_L = 100Ω,
V_OS
Offset Voltage
Single-ended
R_L = 100Ω
CMLOUTP,
CMLOUTN
R_T
Internal Termination Resistor
CMLOUTP,
CMLOUTN
SUPPLY CURRENT
I_DD1
I_DDIO1
I_DDZ
I_DDIOZ
Deserializer
Supply Current
(includes load current)
Deserializer Supply Current
Power Down
Checker Board
Pattern, OS_PCLK/
DATA = H,
EQ = 001,
SSCG=ON
CMLOUTP/N =
enabled
C_L = 4pF, Figure 9
PDB = 0V, All other
LVCMOS Inputs = 0V
V_DD= 1.89V All V_DD pins
V_DDIO=1.89V
V_DDIO = 3.6V ^VDDIO
V_DD= 1.89V
V_DDIO=1.89V
V_DDIO = 3.6V
All V_DD pins
V_DDIO
Recommended Serializer Timing for PCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_TCP
t_TCIH
t_TCIL
t_CLKT
SSC_IN
Transmit Input PCLK Period 5 MHz to 65 MHz, Figure 4
Transmit Input PCLK High Time
Transmit Input PCLK Low Time
PCLK Input Transition Time
PCLK Input – Spread Spectrum fmod
at PCLK = 65 MHz
fdev
Min
+50
−50
-15
80
80
Min
15.38
0.4T
0.4T
0.5
Typ
1.2
542
1.4
93
33
62
40
5
300
Typ
T
0.5T
0.5T
Max Units
mV
mV
V
+15
µA
120
Ω
mV
V
120
Ω
105 mA
45
mA
75
mA
2000 µA
100
µA
2500 µA
Max
200
0.6T
0.6T
2.4
35
±2
Units
ns
ns
ns
ns
kHz
%
13
www.national.com