DS90UR905Q Datasheet, PDF (16/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Symbol
Parameter
BIST Mode
t_PASS
BIST PASS Valid Time,
BISTEN = 1, Figure 17
SSCG Mode
f_DEV
Spread Spectrum
Clocking Deviation
Frequency
f_MOD
Spread Spectrum
Clocking Modulation
Frequency
Conditions
Pin/Freq.
Under typical conditions
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
Under typical conditions
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
Recommended Timing for the Serial Control Bus
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
f_SCL
SCL Clock Frequency
Standard Mode
Fast Mode
t_LOW
SCL Low Period
Standard Mode
Fast Mode
t_HIGH SCL High Period
Standard Mode
Fast Mode
t_HD;STA
Hold time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
t_SU:STA
Set Up time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
t_HD;DAT Data Hold Time,
Figure 18
Standard Mode
Fast Mode
t_SU;DAT Data Set Up Time,
Figure 18
Standard Mode
Fast Mode
t_SU;STO Set Up Time for STOP
Condition, Figure 18
Standard Mode
Fast Mode
t_BUF
Bus Free Time
Standard Mode
Between STOP and START, _{Fast Mode}
Figure 18
t_r
SCL & SDA Rise Time,
Figure 18
Standard Mode
Fast Mode
t_f
SCL & SDA Fall Time,
Figure 18
Standard Mode
Fast mode
Min Typ Max Units
1
10
us
±0.5
±2
%
8
100 kHz
Min Typ Max Units
>0
100 kHz
>0
400 kHz
4.7
us
1.3
us
4.0
us
0.6
us
4.0
us
0.6
us
4.7
us
0.6
us
0
3.45
us
0
0.9
us
250
ns
100
ns
4.0
us
0.6
us
4.7
us
1.3
us
1000 ns
300
ns
300
ns
300
ns
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