DS90UR905Q Datasheet, PDF (26/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Optional BIST Mode
Please see the following section on the chipset BIST mode
for details.
DESERIALIZER FUNCTIONAL DESCRIPTION
The Des converts a single input serial data stream to a wide
parallel output bus, and also provides a signal check for the
chipset Built In Self Test (BIST) mode. The device can be
configured via external pins and strap pins or through the op-
tional serial control bus. The Des features enhance signal
quality on the link by supporting: an equalizer input and also
the FPD-Link II data coding that provides randomization,
scrambling, and DC balanacing of the data. The Des includes
multiple features to reduce EMI associated with display data
transmission. This includes the randomization and scram-
bling of the data and also the output spread spectrum clock
generation (SSCG) support. The Des features power saving
features with a power down mode, and optional LVCMOS (1.8
V) interface compatibility.
Signal Quality Enhancers
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial
stream to increase the eye opening to the Des input. Note this
function cannot be seen at the RxIN+/- input but can be ob-
served at the serial test port (CMLOUTP/N) enabled via the
Serial Bus control registers. The equalization feature may be
controlled by the external pin or by register.
TABLE 5. Receiver Equalization Configuration Table
EQ3
INPUTS
EQ2
EQ1
EQ0
Effect
L
L
L
H
~1.5 dB
L
L
H
H
~3 dB
L
H
L
H
~4.5 dB
L
H
H
H
~6 dB
H
L
L
H
~7.5 dB
EQ3
H
H
H
X
INPUTS
EQ2
EQ1
EQ0
L
H
H
H
L
H
H
H
H
X
X
L
* Default Setting is EQ = Off
Effect
~9 dB
~10.5 dB
~12 dB
OFF*
EMI Reduction Features
Des — Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK)
of the Des feature a selectable output slew. The DATA ((RGB
[7:0], VS, HS, DE) are controlled by strap pin or register bit
OS_DATA. The PCLK is controlled by strap pin or register bit
OS_PCLK. When the OS_PCLK/DATA = HIGH, the maxi-
mum slew rate is selected. When the OS_PCLK/DATA =
LOW, the minimum slew rate is selected. Use the higher slew
rate setting when driving longer traces or a heavier capacitive
load.
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal ter-
mination. A capacitor may be placed on this pin for additional
common-mode filtering of the differential pair. This can be
useful in high noise environments for additional noise rejec-
tion capability. A 0.1µF capacitor may be connected to this
pin to Ground.
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum
clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI.
Output SSCG deviations to ±2.0% (4% total) at up to 35kHz
modulations nominally are available. See Table 6. This fea-
ture may be controlled by external STRAP pins or by register.
TABLE 6. SSCG Configuration (LF_MODE = L) — Des Output
SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
SSC[3:0] Inputs
LF_MODE = L (20 - 65 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
fdev (%)
Off
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
Result
fmod (kHz)
Off
PCLK/2168
PCLK/1300
PCLK/868
PCLK/650
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