DS90UR905Q Datasheet, PDF (31/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

FIGURE 27. OP_LOW Manual Set/Reset
30102066
Des — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on.
If RFB is High, output data is strobed on the Rising edge of
the PCLK. If RFB is Low, data is strobed on the Falling edge
of the PCLK. This allows for inter-operability with downstream
devices. The Des output does not need to use the same edge
as the Ser input. This feature may be controlled by the exter-
nal pin or by register.
Des — Control Signal Filter — Optional
The Des provides an optional Control Signal (VS, HS, DE)
filter that monitors the three video control signals and elimi-
nates any pulses that are 1 or 2 PCLKs wide. Control signals
must be 3 pixel clocks wide (in its HIGH or LOW state, re-
gardless of which state is active). This is set by the CONFIG
[1:0] or by the Control Register. This feature may be controlled
by the external pin or by Register.
Des — Low Frequency Optimization (LF_Mode)
Text to come. This feature may be controlled by the external
pin or by Register.
Des — Map Select
Text to come. This feature may be controlled by the external
pin or by Register.
TABLE 11. Map Select Configuration
INPUTS
Effect
MAPSEL1
L
MAPSEL0
L
Bit 4, Bit 5 on LSB
DEFAULT
L
H
LSB 0 or 1
H
H or L
LSB 0
Des — Strap Input Pins
Configuration of the device maybe done via configuration in-
put pins and the STRAP input pins, or via the Serial Control
Bus. The STRAP input pins share select parallel bus output
pins. They are used to load in configuration values during the
initial power up sequence of the device. Only a pull-up on the
pin is required when a HIGH is desired. By default the pad
has an internal pull down, and will bias Low by itself. The rec-
ommended value of the pull up is 10 kΩ to V_DDIO; open (NC)
for Low, no pull-down is required (internal pull-down). If using
the Serial Control Bus, no pull ups are required.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus
Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode
for details.
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