DS90UR905Q Datasheet, PDF (36/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

TABLE 15. DESERIALIZER — Serial Bus Control Registers
ADD ADD Register Name Bit(s)
(dec) (hex)
0 0 Des Config 1
7
6
5
4
3:2
1
0
1 1 Slave ID
7
6:0
2 2 Des Features 1 7
6
5:4
3
2:0
R/W Defa Function
ult
(bin)
R/W 0 LFMODE
R/W 0 OS_PCLK
R/W 0 OS_DATA
R/W 0 RFB
R/W 00 CONFIG
R/W 0 SLEEP
R/W 0 REG Control
R/W 0
R/W 1110 ID[X]
000
R/W 0 OP_LOW
Release/Set
R/W 0 OSS_SEL
R/W 00 MAP_SEL
R/W 0 OP_LOW strap
bypass
R/W 00 OSC_SEL
Description
0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
0: Normal PCLK Output Slew
1: Increased PCLK Slew
0: Normal DATA OUTPUT Slew
1: Increased Data Slew
0: Data strobed on Falling edge of PCLK
1: Data strobed on Rising edge of PCLK
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Backwards Compatible (DS90UR241)
11: Backwards Compatible (DS90C241)
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0: Configurations set from control pins / STRAP pins
1: Configurations set from registers (except I2C_ID)
0: Address from ID[X] Pin
1: Address from Register
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
0: set outputs state LOW (except LOCK)
1: release output LOW state, outputs toggling normally
Note: This register only works during LOCK = 1.
Output Sleep State Select
0: PCLK/RGB[7:0]/HS/VS/DE = Tri-State, LOCK =
Normal, PASS = H
1: PCLK/RGB[7:0]/HS/VS/DE = L, LOCK = Normal,
PASS = H
Special for Backwards Compatible Mode with
DS90UR241)
00: bit 4, 5 on LSB
01: LSB zero or one
10: LSB zero
11: LSB zero
0: strap will determine whether OP_LOW feature is ON
or OFF
1: Turns OFF OP_LOW feature
000: OFF
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
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