DS90UR905Q Datasheet, PDF (39/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Figure 35 shows a typical application of the DS90UR906Q
Des in Pin/STRAP control mode for a 65 MHz 24-bit Color
Display Application. The LVDS inputs utilize 100 nF coupling
capacitors to the line and the Receiver provides internal ter-
mination. Bypass capacitors are placed near the power sup-
ply pins. At a minimum, seven 0.1 µF capacitors and two 4.7
µF capacitors should be used for local device bypassing. Sys-
tem GPO (General Purpose Output) signals control the PDB
and the BISTEN pins. In this application the RRFB pin is tied
Low to strobe the data on the falling edge of the PCLK.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up
resistors are used on the parallel output bus to select the de-
sired device features. CONFIG[1:0] is set to 01'b for Normal
Mode and Control Signal Filter ON, this is accomplished with
the STRAP pull-up on B7. The receiver input equalizer is also
enabled and set to provide 7.5 dB of gain, this is accomplished
with EQ[3:0] set to 1001'b with STRAP pull ups on G4 and
G7. To reduce parallel bus EMI, the SSCG feature is enabled
and set to 30 kHz and ±1% with SSC[3:0] set to 0010'b and
a STRAP pull-up on R4. The desired features are set with the
use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS lev-
els, thus the VDDIO pin is connected to the 3.3 V rail. The
optional Serial Bus Control is not used in this example, thus
the SCL, SDA and ID[x] pins are left open. A delay cap is
placed on the PDB signal to delay the enabling of the device
until power is stable.
FIGURE 35. DS90UR906Q Typical Connection Diagram — Pin Control
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