DS90UR905Q Datasheet, PDF (15/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
t_RCP
PCLK Output Period
t_RDC
PCLK Output Duty Cycle
t_RCP = t_TCP
SSCG=OFF, 5–65MHz
SSCG=ON, 5–20MHz
PCLK
PCLK
SSCG=ON, 20–65MHz
t_CLH
LVCMOS
Low-to-High
Transition Time, Figure 10
t_CHL
LVCMOS
High-to-Low
Transition Time, Figure 10
V_DDIO = 1.8V,
C_L = 4 pF
PCLK/RGB[7:0], HS,
VS, DE
V_DDIO = 3.3V
C_L = 4 pF
V_DDIO = 1.8V
PCLK/RGB[7:0], HS,
C_L = 4 pF, OS_PCLK/DATA VS, DE
=L
V_DDIO = 3.3V
C_L = 4 pF, OS_PCLK/DATA
=H
t_ROS
t_ROH
t_DDLT
Data Valid before PCLK – Set
Up Time, Figure 14
Data Valid after PCLK – Hold
Time, Figure 14
Deserializer Lock Time,
Figure 13
V_DDIO = 1.71 to 1.89V or 3.0 RGB[7:0], HS, VS, DE
to 3.6V
C_L = 4pF (lumped load)
V_DDIO = 1.71 to 1.89V or 3.0 RGB[7:0], HS, VS, DE
to 3.6V
C_L = 4pF (lumped load)
SSC[3:0] = 0000 (OFF), PCLK = 5MHz
(Note 6)
SSC[3:0] = 0000 (OFF),
(Note 6)
PCLK = 65 MHz
SSC[3:0] = ON,
(Note 6)
PCLK = 5MHz
SSC[3:0] = ON,
(Note 6)
PCLK = 65 MHz
t_DD
Des Delay - Latency,
Figure 11
SSC[3:0] = 0000 (OFF),
(Note 6)
t_DPJ
Des Period Jitter
SSC[3:0] = OFF,
(Note 8), (Note 11)
PCLK = 5MHz
PCLK = 10MHz
PCLK = 65 MHz
t_DCCJ Des Cycle-to-Cycle Jitter
SSC[3:0] = OFF,
(Note 9), (Note 11)
PCLK = 5MHz
PCLK = 10MHz
PCLK = 65 MHz
t_IJT
Des Input Jitter Tolerance,
EQ = OFF,
Figure 16
SSCG = OFF,
PCLK = 65MHz
for jitter freq < 2MHz
for jitter freq > 6MHz
Min Typ
15.38
T
45
50
35
59
40
53
2.1
Max Units
200
ns
55
%
65
%
60
%
ns
2.0
ns
1.6
ns
1.5
ns
0.30 0.45
T
0.40 0.55
T
3
ms
4
ms
30
ms
6
ms
139*T 140*T T
975 1700 ps
500 1000 ps
550 1250 ps
675 1150 ps
375
900
ps
500 1150 ps
0.9
UI
0.5
UI
15
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