DS90UR905Q Datasheet, PDF (42/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Typical Performance Curves
• LVCMOS VOL/IOL (VDDIO, OS_PCLK/DATA, PCLK/
outputs)
• LVCMOS VOH/IOH (VDDIO, OS_PCLK/DATA, PCLK/
outputs)
• Ser ICC
• Des ICC
• SigCon Ser
• SigCon Des
• Cable Length
Revision History
• 2/01/2010
• DS90UR905Q DATASHEET LIMITS HAVE BEEN
UPDATED PER CHARACTERIZATION RESULT AND
ARE THE FINAL LIMITS
• Updated TABLE 12: deleted ID[x] Address 7'b 110 1000
(h'68) (8'b 1101 0000 (h'D0))
• Updated TABLE 13: deleted ID[x] Address 7'b 111 0000
(h'70) (8'b 1110 0000 (h'E0))
• Updated DS90UR906Q Pin Diagram: strap changes on
pin11, pin14, and pin42
• Updated DS90UR906Q Deserializer Pin Descriptions:
RDS feature changed to OS_PCLK and OS_DATA.
Added OP_LOW feature.
• Changed strap pin 14 feature from “RDS” to
“OS_DATA” (Output Slew_DATA)
• Added strap to pin 11 “OS_PCLK” (Output Slew_PCLK)
• Added strap to pin 42 “OP_LOW” (Output LOW)
• Changed Table 14: ADD \ 1 \ bit \ 6:0 \ ID[x]: deleted Device
ID 7b'1101 00 (h'68). Only four (4) IDs will be available.
• Changed Table 15: ADD \ 0 \ bit \ 6 \ OSS_SEL:
“OSS_SEL” changed feature to “OS_PCLK” (Output
Slew_PCLK). OSS_SEL moved to ADD \ 2 \ bit \ 6 \.
• Changed Table 15: ADD \ 0 \ bit \ 5 \ RDS: changed “RDS”
feature to OS_DATA (Output Slew_DATA)
• Changed Table 15: ADD \ 1\ bit \ 6:0 \ ID[x]: deleted Device
ID 7b'1110 00 (h'70). Only four (4) IDs will be available.
• Changed Table 15: ADD \ 2 \ bit \ 7 \ Reserved: changed
“Reserved” to “OP_LOW”
• Changed Table 15: ADD \ 2 \ bit \ 6 \ Reserved: changed
“Reserved” to “OSS_SEL”
• Updated DS90UR905Q Typical Connection Diagram —
Pin Control. Ref 30102044
• Updated DS90UR906Q Typical Connection Diagram —
Pin Control. Ref 30102045
• Created OP_LOW timing figure 26. Ref 30102065.
• Created OP_LOW timing figure27. Ref 30102066.
• Removed IDDT3 and IDDIOT3 (RANDOM pattern)
because the limits are the same as checker board pattern.
• 2/08/2010
• Minor corrections: Changed Iin from +/-10uA to +/-15uA in
Serial Control bus section; added note 11 to: t_XZR, t_PLD,
t_SD, t_DJIT and VOL (in Serial Control Bus Characteristics).
• 2/09/2010
• Added “Note: During initial power-up, a delay of 10ms will
be required before the I2C will respond.” in Optional Serial
Bus Control description section.
• 2/11/2010
• Removed Note 11 on t_DJIT and max values.
• 3/5/2010
• Added reference to soldering profile.
• Added ESD CDM and ESD MM values.
• Updated θ_JA value.
• 5/25/2010
• DS90UR906 DATASHEET LIMITS HAVE BEEN
UPDATED PER CHARACTERIZATION RESULTS
• Corrected TABLE 14. SERIALIZER — Serial Bus Control
Regeisters: register 5 from RFB to VODSEL and register
4 from VODSEL to RFB
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