DS90UR905Q Datasheet, PDF (38/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Applications Information
DISPLAY APPLICATION
The DS90UR905Q/906Q chipset is intended for interface be-
tween a host (graphics processor) and a Display. It supports
an 24-bit color depth (RGB888) and up to 1024 X 768 display
formats. In a RGB888 application, 24 color bits (R[7:0], G[7:0],
B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and
DE) are supported across the serial link with PCLK rates from
5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose
signals may also be sent from host to display.
The Des is expected to be located close to its target device.
The interconnect between the Des and the target device is
typically in the 1 to 3 inch separation range. The input capac-
itance of the target device is expected to be in the 5 to 10 pF
range. Care should be taken on the PCLK output trace as this
signal is edge sensitive and strobes the data. It is also as-
sumed that the fanout of the Des is one. If additional loads
need to be driven, a logic buffer or mux device is recom-
mended.
TYPICAL APPLICATION CONNECTION
Figure 34 shows a typical application of the DS90UR905Q
Ser in Pin control mode for a 65 MHz 24-bit Color Display
Application. The LVDS outputs require 100 nF AC coupling
capacitors to the line. The line driver includes internal termi-
nation. Bypass capacitors are placed near the power supply
pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF ca-
pacitor should be used for local device bypassing. System
GPO (General Purpose Output) signals control the PDB and
BISTEN pins. In this application the RFB pin is tied Low to
latch data on the falling edge of the PCLK. The application
assumes the companion Des (DS90UR906Q) therefore the
configuration pins are also both tied Low. In this example the
cable is long, therefore the VODSEL pin is tied High and a
De-Emphasis value is selected by the resistor R1. The inter-
face to the host is with 1.8 V LVCMOS levels, thus the VDDIO
pin is connected also to the 1.8V rail. The Optional Serial Bus
Control is not used in this example, thus the SCL, SDA and
ID[x] pins are left open. A delay cap is placed on the PDB
signal to delay the enabling of the device until power is stable.
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FIGURE 34. DS90UR905Q Typical Connection Diagram — Pin Control
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