DS90UR905Q Datasheet, PDF (7/44 Pages) National Semiconductor (TI) – 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR906Q Deserializer Pin Descriptions
Pin Name
Pin #
I/O, Type Description
LVCMOS Parallel Interface
R[7:0]
33, 34, 35, I, STRAP, RED Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
36, 37, 39, O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These
40, 41
pins are inputs during power-up (See STRAP Inputs).
G[7:0]
20, 21, 22, I, STRAP, GREEN Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
23, 25, 26, O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These
27, 28
pins are inputs during power-up (See STRAP Inputs).
B[7:0]
9, 10, 11, I, STRAP, BLUE Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
12, 14, 17, O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These
18, 19
pins are inputs during power-up (See STRAP Inputs).
HS
8
O, LVCMOS Horizontal Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to
2 transitions per 130 PCLKs.
VS
7
O, LVCMOS Vertical Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Video
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
DE
6
O, LVCMOS Data Enable Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to
2 transitions per 130 PCLKs.
PCLK
5
O, LVCMOS Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Strobe
edge set by RFB function.
LOCK
32
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS,
VS, DE and PCLK output states are controlled by OSS_SEL (See Table 8). May be used
as Link Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to V_DDIO; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
power-up and set device configuration. Pin Number listed along with shared RGB Output name in square brackets.
CONFIG[1:0]
10 [B6],
9 [B7]
STRAP Operating Modes — Pin or Register Control
I, LVCMOS These pins determine the DS90UR906’s operating mode and interfacing device.
w/ pull-down CONFIG[1:0] = 00: Interfacing to DS90UR905, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905, Control Signal Filter ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241
CONFIG[1:0] = 11: Interfacing to DS90C241
LF_MODE
12 [B4]
STRAP SSCG Low Frequency Mode — Pin or Register Control
I, LVCMOS Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE
w/ pull-down (X).
LF_MODE = 1, SSCG in low frequency mode (PCLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (PCLK = 20-65 MHz)
7
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