COP87L88EB Datasheet, PDF (9/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Pin Description
V_CC and GND are the power supply pins.
CKI is the clock input. The clock can come from a crystal os-
cillator (in conjunction with CKO). See Oscillator Description
section.
RESET is the master reset input. See Reset Description sec-
tion.
The device contains seven bidirectional 8-bit I/O ports (C, E,
F, G, L, M, N) where each individual bit may be indepen-
dently configured as an input (Schmitt trigger inputs on all
ports), output or TRI-STATE under program control. Three
data memory address locations are allocated for each of
these I/O ports. Each I/O port has two associated 8-bit
memory mapped registers, the CONFIGURATION register
and the output DATA register. A memory mapped address is
also reserved for the input pins of each I/O port. (See the
memory map for the various addresses associated with the
I/O ports.) Figure 5 shows the I/O port configurations for the
device. The DATA and CONFIGURATION registers allow for
each port bit to be individually configured under software
control as shown below:
Configuration Data
Port Set-Up
Register
Register
0
0
Hi-Z Input
(TRI-STATE Output)
0
1
Input with Weak Pull-Up
1
0
Push-Pull Zero Output
1
1
Push-Pull One Output
Port L and M are 8-bit I/O ports, they support Multi-Input
Wake-up (MIWU) on all eight pins. All L-pins and M-pins
have Schmitt triggers on the inputs.
Port L and M only have one (1) interrupt vector.
DS100044-6
FIGURE 5. I/O Port Configurations
Port L has the following alternate features:
L7 MIWU
L6 MIWU
L5 MIWU
L4 MIWU
L3 MIWU or RDX
L2 MIWU or TDX
L1 MIWU or CKX
L0 MIWU
Port G is an 8-bit port with 5 I/O pins (G0–G5), an input pin
(G6), and one dedicated output pin (G7). Pins G0–G6 all
have Schmitt Triggers on their inputs. G7 serves as the dedi-
cated output pin for the CKO clock output. There are two reg-
isters associated with the G Port, a data register and a con-
figuration register. Therefore, each of the 6 I/O bits (G0–G5)
can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin the associated bits in the data and configu-
ration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeroes.
Note that the chip will be placed in the HALT mode by wirting
a ’’1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock
Config. Reg.
Data Reg.
G7
CLKDLY
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer I/O)
G2 (Timer T1 Capture Input)
G1 Dedicated WATCHDOG output
G0 INTR (External Interrupt Input)
Port G has the following dedicated function:
G7 CKO Oscillator dedicated output
Port M is a bidirectional I/O, it may be configured in software
as Hi-Z input, weak pull-up, or push-pull output. These pins
may be used as general purpose input/output pins or for se-
lected altlernate functions.
Port M pins have optional alternate functions. Each pin
(M0–M5) has been assigned an alternate data, configura-
tion, or wakeup source. If the respective alternate function is
selected the content of the associated bits in the configura-
tion and/or data register are ignored. If an alternate wakeup
source is selected the input level at the respective pin will be
ignored for the purpose of triggering a wakeup event, how-
ever it will still be possible to read that pin by accessing the
input register. The SPI (Serial Peripheral Interface) block, for
example, uses four of the Port M pins to automatically re-
configure its MISO (Master Input, Slave Output), MOSI
(Master Output, Slave Input), SCK (Serial Clock) and Slave-
Select pins as inputs or outputs, depending on whether the
interface has been configured as a Master or Slave. When
the SPI interface is disabled those pins are available as gen-
eral purpose I/O pins configurable by user software writing to
the associated data and configuration bits. The CAN inter-
face on the device makes use of one of the Port M’s alter-
nate wake-ups, to trigger a wakeup if such a condition has
been detected on the CAN’s dedicated receive pins.
Port M has the following alternate pin functions:
M7 Multi-input Wakeup or CAN
M6 Multi-input Wakeup
M5 Multi-input Wakeup or T2B
9
www.national.com