COP87L88EB Datasheet, PDF (19/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Multi-Input Wakeup (Continued)
ceive wakeup condition. The CAN block has it’s own, dedi-
cated receiver interrupt upon receive buffer full (see CAN
Section).
CAN Wake-Up:
The CAN interface can be programmed to wake the device
from HALT/IDLE mode. This is done by setting bit 7 in the
Port M wake-up enable register (MWKEN). A transition on
the bus will cause the bit 7 of the Port M wake-up pending
(MWKPND) to be set and thereby waking up the device. The
frame on the CAN bus will be lost. The MWEDG (m port
wake-up edge) register bit 7 can be programmed high or low
(high will wake-up on the first falling edge on Rx0).
Resetting bit 7 in the MWKEN will disable the CAN wake-up.
The following sequence should be executed before entering
HALT/IDLE mode:
RBIT 7, MWKPND ;clear CAN wake-up pending
LD A, CBUS
AND A, #0CF
X A, CBUS
;resetTxEN0 and TxEN1
;disable main receive
;comparator
After the device woke-up the CBUS bits TxEN0 and/or
TxEN1 need be set to allow synchronization on the bus and
to enable transmission/reception of CAN frames.
CAN Block Description *
This device contains a CAN serial bus interface as described
in the CAN Specification Rev. 2.0 part B.
*Patents Pending.
CAN Interface Block
This device supports applications which require a low speed
CAN interface. It is designed to be programmed with two
transmit and two receive registers. The user’s program may
check the status bytes in order to get information of the bus
state and the received or transmitted messages. The device
has the capability to generate an interrupt as soon as one
byte has been transmitted or received. Care must be taken if
more than two bytes in a message frame are to be
transmitted/received. In this case the user’s program must
poll the transmit buffer empty (TBE)/receive buffer full (RBF)
bits or enable their respective interrupts and perform a data
exchange between the user data and the Tx/Rx registers.
Fully automatic transmission on error is supported for mes-
sages not longer than two bytes. Messages which are longer
than two bytes have to be processed by software.
The interface is compatible with CAN Specification 2.0 part
B, without the capability to receive/transmit extended
frames. Extended frames on the bus are checked and ac-
knowledged according to the CAN specification.
The maximum bus speed achievable with the CAN interface
is a function of crystal frequency, message length and soft-
ware overhead. The device can support a bus speed of up to
1 Mbit/s with a 10 MHz oscillator and 2 byte messages. The
1 Mbit/s bus speed refers to the rate at which protocol and
data bits are transferred on the bus. Longer messages re-
quire slower bus speeds due to the time required for soft-
ware intervention between data bytes. The device will sup-
port a maximum of 125k bit/s with eight byte messages and
a 10 MHz oscillator.
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