COP87L88EB Datasheet, PDF (22/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Functional Block Description of
the CAN Interface (Continued)
Output Drivers/Input Comparators
The output drivers/input comparators are the physical inter-
face to the bus. Control bits are provided to TRI-STATE the
output drivers.
A dominant bit on the bus is represented as a “0” in the data
registers and a recessive bit on the bus is represented as a
“1” in the data registers.
TABLE 4. Bus Level Definition
Bus Level
“dominant”
“recessive”
Pin Tx0
drive low
(GND)
TRI-STATE
Pin Tx1
dirve high
(V_CC)
TRI-STATE
Data
0
1
Register Block
The register block consists of fifteen 8-bit registers which are
described in more detail in the following paragraphs.
Note: The contents of the receiver related registers RxD1, RxD2, RDLC,
RIDH and RTSTAT are only changed if a received frame passes the
acceptance filter or the Receive Identifier Acceptance Filter bit (RIAF)
is set to accept all received messages.
TRANSMIT DATA REGISTER 1 (TXD1) (Address
X’00A0)
The Transmit Data Register 1 contains the first data byte to
be transmitted within a frame and then the successive odd
byte numbers (i.e., bytes number 1,3,..,7).
TRANSMIT DATA REGISTER 2 (TXD2)(Address X’00A1)
The Transit Data Register 2 contains the second data byte to
be transmitted within a frame and then the successive even
byte numbers (i.e., bytes number 2,4,..,8).
TRANSMIT DATA LENGTH CODE AND IDENTIFIER
LOW REGISTER (TDLC) (Address X’00A2)
TID3 TID2 TID1 TID0 TDLC3 TDLC2 TDLC1 TDLC0
Bit 7
Bit 0
This register is read/write.
TID3..TIDO Transmit Identifier Bits 3..0 (lower 4 bits)
The transmit identifier is composed of eleven bits in total, bits
3 to 0 of the TID are stored in bits 7 to 4 of this register.
TDLC3..TDLC0 Transmit Data Length Code
These bits determine the number of data bytes to be trans-
mitted within a frame. The CAN specification allows a maxi-
mum of eight data bytes in any message.
TRANSMIT IDENTIFIER HIGH (TID) (Address X’00A3)
TRTR TID10 TID9 TID8 TID7 TID6 TID5 TID4
Bit 7
Bit 0
This register is read/write.
TRTR Transmit Remote Frame Request
This bit is set if the frame to be transmitted is a remote frame
request.
TID10..TID4 Transmit Identifier Bits 10 .. 4 (higher 7 bits)
Bits TID10..TID4 are the upper 7 bits of the 11 bit transmit
identifier.
RECEIVER DATA REGISTER 1 (RXD1) (Address
X’00A4)
The Receive Data Register 1 (RXD1) contains the first data
byte received in a frame and then successive odd byte num-
bers (i.e., bytes 1, 3,..7). This register is read-only.
RECEIVE DATA REGISTER 2 (RXD2) (Address X’00A5)
The Receive Data Register 2 (RXD2) contains the second
data byte received in a frame and then successive even byte
numbers (i.e., bytes 2,4,..,8). This register is read-only.
REGISTER DATA LENGTH CODE AND IDENTIFIERLOW
REGISTER (RIDL) (Address X’00A6)
RID3 RID2 RID1 RID0 RDLC3 RDLC2 RDLC1 RDLC0
Bit 7
Bit 0
This register is read only.
RID3..RID0 Receive Identifier bits (lower four bits)
The RID3..RID0 bits are the lower four bits of the eleven bit
long Receive Identifier. Any received message that matches
the upper 7 bits of the Receive Identifier (RID10..RID4) is ac-
cepted if the Receive Identifier Acceptance Filter (RIAF) bit is
set to zero.
RDLC3..RDLC0 Receive Data Length Code bits
The RDLC3..RDLC0 bits determine the number of data
bytes within a received frame.
RECEIVE IDENTIFIER HIGH (RID) (Address X’00A7)
Reserved RID10 RID9 RID8 RID7 RID6 RID5 RID4
Bit 7
Bit 0
This register is read/write.
Bit 7 is reserved and should be zero.
RID10..RID4 Receive Identifier bits (upper bits)
The RID10...RID4 bits are the upper 7 bits of the eleven bit
long Receive Identifier. If the Receive Identifier Acceptance
Filter (RIAF) bit (see CBUS register) is set to zero, bits 4 to
10 of the received identifier are compared with the mask bits
of RID4..RID10. If the corresponding bits match, the mes-
sage is accepted. If the RIAF bit is set to a one, the filter
function is disabled and all messages, independent of iden-
tifier, will be accepted.
CAN PRESCALER REGISTER (CSCAL) (Address
X’00A8)
CKS7 CKS6 CKS5 CKS4 CKS3 CKS2 CKS1 CKS0
Bit 7
Bit 0
This register is read/write.
CKS7..0 Prescaler divider select.
The resulting clock value is the CAN Prescaler clock.
CAN BUS TIMING REGISTER (CTIM) (00A9)
PPS2 PPS1 PPS0 PS2 PS1 PS0 Reserved Reserved
Bit 7
Bit 0
This register is read/write.
PPS2..PPS0 Propagation Segment, bits 2..0
The PPS2..PPS0 bits determine the length of the propaga-
tion delay in Prescaler clock cycles (PSC) per bit time. (For
a more detailed discussion of propagation delay and phase
segments, see SYNCHRONIZATION.)
PS2..PS0 Phase Segment 1, bits 2..0
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