COP87L88EB Datasheet, PDF (6/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

DC Electrical Characteristics (Continued)
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V_CC or GND, and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to V_CC; Port C, G, E, F, L, M and N I/Os con-
figured as outputs and programmed low; D outputs programmed high. Parameter refers to HALT mode entered via setting bit 7 of the Port G data register. Part will
pull up CKI during HALT in crystal clock mode. Both CAN main comparator and the CAN Wakeup comparator need to be disabled.
Note 5: . HALT and IDLE current specifications assume CAN block comparators are disabled.
Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V_CC and the pins will have sink current
to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 7: Condition and parameter valid only for part in HALT mode.
Note 8: Parameter characterized but not tested.
AC Electrical Characteristics
−40˚C ≤ T_A ≤ +85˚C
Parameter
Instruction Cycle Time (t_c)
Crystal/Resonator
Inputs
t_SETUP
t_HOLD
Output Propagation Delay (t_PD1, t_PD0) (Note 9)
SK, SO
All others
MICROWIRE
Setup Time (tUWS) (Note 10)
Hold Time (tUWH) (Note 10)
Output Pop Delay (tUPD)
Input Pulse Width
Interrupt High Time
Interrupt Low Time
Timer 1, 2 High Time
Timer 1, 2 Low Time
Reset Pulse Width (Note 10)
Conditions
V_CC ≥ 4.5V
V_CC ≥ 4.5V
V_CC ≥ 4.5V
C_L = 100 pF, R_L = 2.2 kΩ
V_CC ≥ 4.5V
V_CC ≥ 4.5V
Min
Typ
Max
Units
1.0
DC
µs
200
ns
60
ns
0.7
µs
1
µs
20
ns
56
ns
220
ns
1
t_c
1
t_c
1
t_c
1
t_c
1.0
µs
t_c = Instruction Cycle Time
The maximum bus speed achievable with the CAN interface is a function of crystal frequency, message length and software overhead. The device can support a bus
speed of up to 1 Mbit/S with a 10 MHz oscillator and 2 byte messages. The 1M bus speed refers to the rate at which protocol and data bits are transferred on the
bus. Longer messages require slower bus speeds due to the time required for software intervention between data bytes. The device will support a maximum of 125k
bits/s with eight byte messages and a 10 MHz oscillator.
For device testing purpose of all AC parameters, V_OH will be tested at 0.5*V_CC.
Note 9: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 10: Parameter not tested.
On-Chip Voltage Reference
−40˚C ≤ T_A ≤ +85˚C
Parameter
Conditions
Min
Reference Voltage
V_REF
Reference Supply
Current, I_DD
I_OUT < 80 µA,
V_CC = 5V
I_OUT = 0A, (No Load)
V_CC = 5V (Note 11)
0.5V_CC −0.12
Note 11: Reference supply I_DD is supplied for information purposes only, it is not tested.
Max
0.5V_CC +0.12
120
Units
V
µA
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