COP87L88EB Datasheet, PDF (66/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Instruction Set (Continued)
INSTRUCTION EXECUTION TIME
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B]
ADD
1/1
ADC
1/1
SUBC
1/1
AND
1/1
OR
1/1
XOR
1/1
IFEQ
1/1
IFGT
1/1
IFBNE
1/1
DRSZ
SBIT
1/1
RBIT
1/1
IFBIT
1/1
RPND
1/1
Direct
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1/3
3/4
3/4
3/4
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
Instructions Using A and C
CLRA
1/1
INCA
1/1
DECA
1/1
LAID
1/3
DCORA
1/1
RRCA
1/1
RLCA
1/1
SWAPA
1/1
SC
1/1
RC
1/1
IFC
1/1
IFNC
1/1
PUSHA
1/3
POPA
1/3
ANDSZ
2/2
Transfer of Control Instructions
JMPL
3/4
JMP
2/3
JP
1/3
JSRL
3/5
JSR
2/5
JID
1/3
VIS
1/5
RET
1/5
RETSK
1/5
RETI
1/5
INTR
1/7
NOP
1/1
Memory Transfer Instructions
X A, (Note *NO
TARGET FOR
FNXref
NS13180*)
LD A, (Note 24)
LD B, Imm
LD B, Imm
LD Mem, Imm
LD Reg, Imm
IFEQ MD, Imm
Register
Indirect
[B] [X]
1/1 1/3
Direct
2/3
Immed.
Register Indirect
Auto Incr. and Decr.
[B+, B−] [X+, X−]
1/2
1/3
1/1
1/3
2/3
2/2
1/2
1/3
1/1
2/3
2/2
3/3
2/2
2/3
3/3
(IF B < 16)
(IF B > 15)
Note 24: = > Memory location addressed by B or X or directly.
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