COP87L88EB Datasheet, PDF (10/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Pin Description (Continued)
M4 Multi-input Wakeup or T2A
M3 Multi-input Wakeup or SS
M2 Multi-input Wakeup or SCK
M1 Multi-input Wakeup or MOSI
M0 Multi-input Wakeup or MISO
Ports C, E, F and N are general-purpose, bidirectional I/O
ports.
Any device package that has Port C, E, F, M, N but has fewer
than eight pins, contains unbonded, floating pads internally
on the chip. For these types of devices, the software should
write a 1 to the configuration register bits corresponding to
the non-existent port pins. This configures the port bits as
outputs, thereby reducing leakage current of the device.
Port N is an 8-bit wide port with alternate function capability
used for extending the slave select (SS) lines of the on SPI
interface. The SPI expander block provides mutually exclu-
sive slave select extension signals (ESS0 to ESS7) accord-
ing to the state of the SS line and specific contents of the SPI
shift register. These slave select extension lines can be
routed to the Port N I/O pins by enabling the alternate func-
tion of the port in the PORTNX register. If enabled, the inter-
nal signal on the ESSx line causes the ports state to change
exactly like a change to the PORTND register. It is the user’s
responsibility to switch the port to an output when enabling
the alternate function.
Port N has the following alternate pin functions:
N7 ESS7
N6 ESS6
N5 ESS5
N4 ESS4
N3 ESS3
N2 ESS2
N1 ESS1
N0 ESS0
CAN pins: For the on-chip CAN interface this device has five
dedicated pins with the following features:
V_REF On-chip reference voltage with the value of V_CC/2
Rx0 CAN receive data input pin.
RX1 CAN receive data input pin.
Tx0 CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN0 bit in the CAN
Bus control register.
Tx1 CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN1 bit in the CAN
Bus control register.
ALTERNATE PORT FUNCTIONS
Many general-purpose pins have alternate functions. The
software can program each pin to be used either for a
general-purpose or for a specific function. The chip hardware
determines which of the pins have alternate functions, and
what those functions are. This section lists the alternate
functions available on each of the pins.
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more port D outputs (ex-
cept D2) together in order to get a higher drive.
Note: Care must be exercised with D2 pin operation. At RESET, the external
loads on this pin must ensure that the output voltages stay above 0.8
V_CC to prevent the chip from entering special modes. Also keep the ex-
ternal loading on D2 to < 1000 pF.
Port I is an 8-bit Hi-Z input port, and also provides the analog
inputs to the A/D converter. If unterminated, Port I pins will
draw power only when addressed.
Functional Description
The architecture of the device utilizes a modified Harvard ar-
chitecture. With the Harvard architecture, the control store
program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t_c) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 02F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory for the device consists of 8 or 32 kbytes of
OTP EPROM. These bytes may hold program instructions or
constant data (data tables for the LAID instruction, jump vec-
tors for the JID instruction and interrupt vectors for the VIS
instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 0FF Hex.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.
Security is an optional feature and can only be asserted after
the memory array has been programmed and verified. A se-
cured part will read all 00(hex) by a programmer. The part
will fail Blank Check and will fail Verify operations. A Read
operation will fill the programmer’s memory with 00(hex).
The Security byte itself is always readable with value of
00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
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