COP87L88EB Datasheet, PDF (23/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Functional Block Description of
the CAN Interface (Continued)
The PS2..PS0 bits fix the number of Prescaler clock cycles
per bit time for phase segment 1 and phase segment 2. The
PS2..PS0 bits also set the synchronization Jump Width to a
value equal to the lesser of: 4 PSC, or the length of PS1/2
(Min: 4 l length of PS1/2).
Bits 1 and 0 are reserved and should be zero.
TABLE 5. Synchronization Jump Width
Length of Synchronization
PS2 PS1 PS0
Phase
Jump Width
Segment ¹â„2
0
0
0
1 t_can
1 t_can
0
0
1
2 t_can
2 t_can
0
1
0
3 t_can
3 t_can
0
1
1
4 t_can
4 t_can
1
0
0
5 t_can
4 t_can
1
0
1
6 t_can
4 t_can
1
1
0
7 t_can
4 t_can
1
1
1
8 t_can
4 t_can
LENGTH OF TIME SEGMENTS (See Figure 28)
• The Synchronization Segment is 1 CAN Prescaler clock
(PSC)
• The Propagation Segment can be programmed (PPS) to
be 1,2...,8 PSC in length.
• Phase Segment 1 and Phase Segment 2 are program-
mable (PS) to be 1,2,..,8 PSC long.
Note: (BTL settings at high speed; PSC = 0) Due to the on-chip delay from
the rx-pins through the receive comparator (worst case assumption: 3
clocks delay * 2 (devices on the bus) + 1 tx delay) the user needs to set
the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com-
munication on the bus under all circumstances. With prescaler settings
of 0 this is a given (i.e., no caution has to be applied).
Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example
for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). − all at 10 MHz
CKI and CSCAL = 0.
CAN BUS CONTROL REGISTER (CBUS) (00AA)
Re- RIAF TxEN1 TxEN0 RxREF1 RxREF0 Re- FMOD
served
served
Bit 7
Bit 0
Reserved These bits are reserved and should be zero.
RIAF
Receive identifier acceptance filter bit
If the RIAF bit is set to zero, bits 4 to 10 of the received iden-
tifier are compared with the mask bits of RID4..RID10 and if
the corresponding bits match, the message is accepted. If
the RIAF bit is set to a one, the filter function is disabled and
all messages independent of the identifier will be accepted.
TxEN0, TxEN1 TxD Output Driver Enable
TxEN1
0
0
1
TABLE 6. Output Drivers
TxEN0
0
1
0
Output
Tx0, Tx1 TRI-STATE, CAN
input comparator disabled
Tx0 enabled
Tx1 enabled
TxEN1
TxEN0
Output
1
1
Tx0 and Tx1 enabled
Bus synchronization of the device is done in the following
way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either
TxEN1 or TxEN0, or both are set to 1, the device will not start
transmission or reception of a frame until eleven consecutive
“recessive” bits have been received. Resetting the TxEN1
and TxEN0 bits will disable the output drivers and the CAN
input comparator. All other CAN related registers and flags
will be unaffected. It is recommended that the user reset the
TxEN1 and TxEN0 bits before switching the device into the
HALT mode (the CAN receive wakeup will still work) in order
to reduce current consumption and to assure a proper resy-
chronization to the bus after exiting the HALT mode.
Note: A “bus off” condition will also cause Tx0 and Tx1 to be at TRI-STATE
(independent of the values of the TxEN1 and TxEN0 bits).
RXREF1 Reference voltage applied to Rx1 if bit is set
RXREF0 Reference voltage applied to Rx0 if bit is set
FMOD Fault Confinement Mode select
Setting the FMOD bit to “0” (default after power on reset) will
select the Standard Fault Confinement mode. In this mode
the device goes from “bus off” to “error active” after monitor-
ing 128*11 recessive bits (including bus idle) on the bus. This
mode has been implemented for compatibility with existing
solutions. Setting the FMOD bit to “1” will select the En-
hanced Fault Confinement mode. In this mode the device
goes from “bus off” to “error active” after monitoring 128
“good” messages, as indicated by the reception of 11 con-
secutive “recessive” bits including the End of Frame,
whereas the standard mode may time out after 128 x 11 re-
cessive bits (e.g., bus idle).
TRANSMIT CONTROL/STATUS (TCNTL) (00AB)
NS1 NS0 TERR RERR CEIE TIE RIE TXSS
Bit 7
Bit 0
NS1..NS0 Node Status, i.e., Error Status.
TABLE 7. Node Status
NS1
NS0
Output
0
0
Error active
0
1
Error passive
1
0
Bus off
1
1
Bus off
The Node Status bits are read only.
TERR Transmit Error
This bit is automatically set when an error occurs during the
transmission of a frame. TERR can be programmed to gen-
erate an interrupt by setting the Can Error Interrupt Enable
bit (CEIE). This bit must be cleared by the user’s software.
Note: This is used for messages for more than two bytes. If an error occurs
during the transmission of a frame with more than 2 data bytes, the us-
er’s software has to handle the correct reloading of the data bytes to
the TxD registers for retransmission of the frame. For frames with 2 or
fewer data bytes the interface logic of this chip does an automatic re-
transmission. Regardless of the number of data bytes, the user’s soft-
ware must reset this bit if CEIE is enabled. Otherwise a new interrupt
will be generated immediately after return from the interrupt service
routine.
RERR Receiver Error
This bit is automatically set when an error occurred during
the reception of a frame. RERR can be programmed to gen-
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