COP87L88EB Datasheet, PDF (45/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Serial Peripheral Interface (Continued)
The SPIU Control Register
FIGURE 38. SPI Block Diagram
DS100044-40
Bit 7
SRIE
0
TABLE 13. SPI Control (SPICNTL) (0098)
Bit 6
STIE
0
Bit 5
SESSEN
0
Bit 4 Bit 3
SPIMOD[1:0]
0
0
Bit 2
SCE
0
Bit 1
SPIEN
0
Bit 0
SLOOP
0
B7
SRIE
SPI Receive Interrupt Enable
0 — disable receive interrupt
0 — enable receive interrupt
B6
STIE
SPI Transmit buffer Interrupt Enable
0 — disable transmit buffer interrupt
0 — enable transmit buffer interrupt
B5
SESSEN
SPI SS Expander (ESS) enable
0 — The detection of the ESS programming mode is disabled, i.e., the value of MOSI at the falling
edge of SS is “don’t care”.
1 — ESS programming mode detection is enabled, i.e., if the condition “MOSI = 0 at the falling edge
of SS” occurs, the SS-Expander is selected and bits [7:0] of the first transmitted byte determine the
state of the N-port (ESS[7:0]). ESS[7:0] will go 1 at the positive edge of SS.
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