COP87L88EB Datasheet, PDF (16/72 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART

Power Save Modes
The device offer the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontrol-
ler activities are stopped. In the IDLE mode, the on-board
oscillator circuitry and timer T0 are active but all other mi-
crocontroller activities are stopped. In either mode, all on-
board RAM, registers, I/O states, and timers (with the ex-
ception of T0) are unaltered.
HALT MODE
The device is placed in the HALT mode by writing a ’’1” to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, and timers, are stopped. In the HALT
mode, the power requirements of the device are minimal
and the applied voltage (V_CC) may be decreased to Vr
(Vr = 2.0V) without altering the state of the machine.
CAN HALT/IDLE mode:
In order to reduce the device overall current consumption
in HALT/IDLE mode a two step power save mechanism is
implemented on the device:
Step 1:
Disable main receive comparator. This is done
by resetting both the TxEN0 and TxEN1 bits in
the CBUS register. Note: These bits should al-
ways be reset before entering HALT/IDLE mode
to allow proper resynchronization to the CAN
bus after exiting HALT/IDLE mode.
Step 2:
Disable the CAN wake-up comparators, this is
done by resetting bit 7 in the port-m wakeup en-
able register (MWKEN) a transition on the CAN
bus will then not wake the device up.
Note: If both the main receive comparator and the wake-up comparator
are disabled the on chip CAN voltage reference is also disabled.
The CAN-V_REF output is then High-Z
The following table shows the two CAN power save modes and the active CAN transceiver blocks:
Step 1
0
0
1
1
Step 2
0
1
0
1
Main-Comp
on
on
off
off
Wake-Up-Comp
on
off
on
off
CAN-V_REF
on
on
on
off
V_REF Pin
V_CC/2
V_CC/2
V_CC/2
High-Z
The device supports two different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L & M port. The second
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the t_c instruction cycle clock. The t_c
clock is derived by dividing the oscillator clock down by a fac-
tor of 10. The Schmitt trigger following the CKI inverter on
the chip ensures that the IDLE timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The start-up time-out from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature,
while the second mask option disables the HALT mode. With
the HALT mode enable mask option, the device will enter
and exit the HALT mode as described above. With the HALT
disable mask option, the device cannot be placed in the
HALT mode (writing a “1” to the HALT flag will have to effect).
IDLE MODE
The device is placed in the IDLE mode by writing a “1” to the
IDLE flag (G6 data bit). In this mode, all activity, except the
associated on-board oscillator circuitry, ad the IDLE Timer
T0, is stopped. The power supply requirements of the micro-
controller in this mode of operation are typically around 30%
of normal power requirement of the microcontroller.
As with the HALT mode, the device can be returned to nor-
mal operation with a reset, or with a Multi-Input Wakeup from
the Port L or CAN Interface. Alternately, the microcontroller
resumes normal operation from the IDLE mode when the
thirteenth bit (representing 4.096 ms at internal clock fre-
quency of 1 MHz, t_c = 1 µs) of the IDLE Timer toggles.
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruciton following the “Enter Idle
Mode” instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the “Enter IDLE Mode” instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately,
the Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 7 edge selectable external interrupts.
Note: The following description is for both the Port L and the M port. When
the document refers to the registers WKEGD, WKEN or WKPND, the
user will have to put either M (for M port) or L (for port) in front of the
register, i.e., LWKEN (Port L WKEN), MWKEN (Port M WKEN).
Figures 12, 13 shows the Multi-Input Wakeup logic for the
microcontroller. The Multi-Input Wakeup feature utilizes the L
Port. The user selects which particular Port L bit (or combi-
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