DS90C387R Datasheet, PDF (6/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

Transmitter Switching Characteristics (Continued)
Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of ±2ns applied to the input clock signal while data inputs are switching (see figures 10 and 11). A jitter event of 2ns, represents worse case jump
in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
Note 7: This limit is based on the capability of deskew circuitry. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on
type/length of cable) and clock jitter. RSKM with deskew is ± 1 LVDS bit time (1/7th clock period) data to clock skew.
Note 8: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT(process, voltage and
temperature) range.
Note 9: From V = 1.5V of CLKINP to V_DIFF= 0V of CLK1P when R_FB = High, DUAL = Low or High, BAL = Low.
DIGITAL SWITCHING CHARACTERISTICS for Two-Wire Serial
Communication Interface
Unless otherwise noted, below specifications apply for V_cc=+3.3V, load capacitance on output lines = 80 pF. Load capacitance
on output lines can be up to 400 pF provided that external pull-up switch is on board. The following parameters are the timing
relationships between SCL and SDA signals related to the DS90C387R.
Symbol
Parameter
Min
Typ
Max
Units
t₁
SCL (Clock) Period
2.5
µs
t₂
Data in Set-Up Time to SCL High
100
ns
t₃
Data Out Stable after SCL Low
0
ns
t₄
SDA Low Set-Up Time to SCL Low (Start Condition)
100
ns
t₅
SDA High Hold Time after SCL High (Stop Condition)
100
ns
AC Timing Diagrams
10128832
FIGURE 1. Two-Wire Serial Communication Interface Timing Diagram when I2CSEL = Vcc
www.national.com
6