DS90C387R Datasheet, PDF (14/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R Pin Description—LDI Transmitter (Continued)
R_FB
VCC
GND
TABLE 2. Relationship between R_FB, DE, HSYNC and VSYNC pins
Primary Edge
Falling
Rising
Secondary Edge
Rising
Falling
DE latches on
Rising
Falling
HSYNC latches on
Falling
Rising
VSYNC latches on
Falling
Rising
Two-Wire Serial Communication Interface Description
The DS90C387R operates as a slave on the Serial Bus, so
the SCL line is an input (no clock is generated by the
DS90C387R) and the SDA line is bi-directional. DS90C387R
has a 7-bit slave address. The address bits are controlled by
the state of the address select pins A2, A1 and A0, and are
set by connecting these pins to ground for a LOW, (0) , to
V_CC for a HIGH, (1).
Therefore, the complete slave address is:
A6 A5 A4 A3 A2 A1 A0
MSB
LSB
and is selected as follows:
Address Select Pin
State
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
DS90C387R Serial
Bus Slave Address
A6:A0 binary
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
The DS90C387R latches the state of the address select pins
during the first read or write on the Serial Bus. Changing the
state of the address select pins after the first read or write to
any device on the Serial Bus will not change the slave
address of the DS90C387R.
A zero in front of the register address is required as the most
left column shown in the table below. For example, to access
register F, “0F” is the correct way of accessing the register.
TABLE 3. Register Mapping(" * ’ = features not implemented on DS90C387R)
Addr
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
Bit7
Bit6
Bit5
Bit4
Bit3
VND_IDL(RO)
VND_IDH(RO)
DEV_IDL(RO)
DEV_IDH(RO)
DEV_REV(RO)
RSVD[7:0](RO)
FRQ_LOW[7:0](RO)
FRQ_HIGH[7:0](RO)
RSVD[1:0]
VEN(RW) HEN(RW) DSEL(RW)
VLOW(RO)
MSEL[2:0](RW)
TSEL(RW)
*DK[3:1](RW)
*DKEN(RW)
*CFG[7:0](RO)
*VDJK[7:0](RW)
RSVD[3:0](RW)
RSVD[7:0](RW)
RSVD[7:0](RW)
Bit2
Bit1
BSEL(RW) EDGE(RW)
RSEN(RO) *HTPLG(RO)
CTL[3:1](RW)
RSVD[3:0](RO)
Bit0
PD(RW)
MDI(RW)
RSVD(RW)
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