DS90C387R Datasheet, PDF (12/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R Pin Description—LDI Transmitter (Continued)
Pin Name
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
CLK2P/NC
CLK2M/NC
V_REF
I/O
I
I
I
I
O
O
I
I2CSEL
I
DDREN/I2Cclk
I
DSEL/I2Cdat
I/O
A0
I
A1
I
A2
I
MSEN
O
TST1
TST2
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
No.
Description
2
Connect to power supply with voltage stated under ” Recommended
Operating Conitions ” on page 3. Power supply pins for PLL circuitry, pin 10,
16.
3
Ground pins for PLL circuitry, pins 14, 15, 17.
3
Connect to power supply with voltage stated under ” Recommended
Operating Conitions ” on page 3. Power supply pins for LVDS outputs, pins
30, 40, 48.
4
Ground pins for LVDS outputs, pins 25, 35, 43, 51.
1
Additional positive LVDS differential clock output identical to CLK1P. No
connect if not used.
1
Additional negative LVDS differential clock output identical to CLK1M. No
connect if not used.
1
V_REF= 1/2 V_DDQ, a ”Fixed “ line of differential input.
If V_REF ≥ 1.8V, indicates input data is in LVTTL mode.
If V_REF < 1.1V, indicates input data is in low voltage swing mode.
In low voltage swing mode, input data = logic HIGH = V_REF + 100mV.
In low voltage swing mode, input data = logic LOW = V_REF - 100mV.
This pin is not to be left floating. When not use in LVTTL mode, tie to V_cc
1
HIGH to enable two-wire serial communication interface; LOW to disable the
interface.
1
Always HIGH for one 12-bit port and two 12-bit ports operation. When
I2CSEL = HIGH, this is the clock line for the two-wire serial communication
interface.
1
Differential select pin for CLKIN (HIGH = single-ended, LOW = differentail)
or when I2CSEL = HIGH, this is the Bidirectional Data line for the two-wire
serial communication interface.
1
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
1
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
1
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
1
Interrupt signal. This is an open drain output, pull-up resistor is required.
1
Test pin, tie to Vcc.
1
Test pin, no connect. Do not tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, no connect. Do not tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
Note 14: Inputs default to “low” when left open due to internal pull-down resistor.
TABLE 1. Control Settings for mode selection
Mode
DUAL
BAL
I2CSEL
DDREN/I2Cclk
CLKIN polarity
12bit
L
L/H
L
H
R_FB
Two 12-bit
H
L/H
L
H
R_FB
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