DS90C387R Datasheet, PDF (26/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

Applications Information (Continued)
feature supports backward compatibility with the previous
generation of devices - the second clock allows the transmit-
ter to interface to panels using a ’dual pixel’ configuration of
two 24-bit or 18-bit ’notebook’ receivers.
Pre-emphasis feature is available for use in both the DC
balanced and non-DC balanced (backwards compatible)
modes.
Information on Jitter Rejection:
The transmitter is designed to reject cycle-to-cycle jitter
which may be seen at the transmitter input clock. Very low
cycle-to-cycle jitter is passed on to the transmitter outputs.
Transmitter Block Diagram
This significantly reduces the impact of jitter provided by the
input clock source, and improves the accuracy of data sam-
pling. Data sampling is further enhanced by automatically
calibrated data sampling strobes at the receiver inputs. Tim-
ing and control signals (VSYNC, HSYNC, DE) are sent
during blanking intervals to guarantee correct reception of
these critical signals.
The transmitter is offered with programmable primary clock
edge for convenient interface with a variety of graphics
controllers. The transmitter can be programmed for rising
edge strobe or falling edge strobe through a dedicated pin. A
rising edge transmitter will inter-operate with a falling edge
receiver without any translation logic.
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Configuration Table
TABLE 12. Transmitter / DS90CF388 Receiver configuration table
Pin
R_FB (Tx only)
R_FDE (both Tx and Rx)
BAL (both Tx and Rx)
DUAL (Tx only)
Condition
R_FB = V_CC
R_FB = GND
R_FDE = V_CC
R_FDE = GND
BAL=V_CC
BAL=Gnd
DUAL=V_CC
DUAL=Gnd
Configuration
Primary clock edge selected as Falling Edge
Primary clock edge selected as Rising Edge
Active data DE = High
Active data DE = Low
DC Balanced enabled
DC Balanced disabled (backward compatible to FPD-Link)
48-bit color (dual pixel) support
24-bit color (single pixel) support
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