DS90C387R Datasheet, PDF (24/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

Applications Information
How to configure the DS90C387R to work with
DS90CF384/DS90CF384A/DS90CF386 or DS90CF388 for
most common application:
1. To configure for single pixel application using the
DS90C387R to interface with GMCH host, please see table
below for reference pin connection and configuration. Due to
the implementation differences among various GMCH ven-
dors, the table is using the GMCH vendor located in Santa
Clara, California, USA as an example. A two-wire serial
communication interface based EEPROM containing EDID
128 bytes LCD timing information may be required depend-
ing on device driver implementation.
From DS90C387R
To GMCH
data signal connection
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
CLKINP
CLK1
CLKINM
CLK0
DE
BLANK
HSYNC
HSYNC
VSYNC
VSYHC
configuration for other pins
DDRENI2Cclk
I2CCLK
DSELI2Cdat
I2CDATA
A0
GND
A1
GND
A2
GND
PLLSEL
Vcc
DUAL
GND
BAL
GND
D12 to D23
No connect
RESERVED1
GND
RESERVED2
GND
RESERVED3
No connect
RESERVED4
GND
RESERVED5
GND
RESERVED6
GND
RESERVED7
GND
RESERVED8
GND
RESERVED9
GND
TST1
Vcc
TST2
No connect
VREF
MSEN
VREF
INT#
2. To configure for single pixel application using the
DS90C387R with single DS90CF384 or DS90CF384A or
DS90CF386 LVDS based LCD panel or monitor, the “DUAL”
pin must be set to Gnd (single RGB), and “BAL” pin must be
set to Gnd to disable the feature for DS90CF384/
DS90CF386 doesn’t support DC balance function. For cable
length more than two meters, pre-emphasis feature is rec-
ommended. Please see table below for reference pin con-
nection.
From DS90C387R Output
To LVDS based LCD
Pins
monitor
data signal connection
A0M
RxIN0−
A0P
RxIN0+
A1M
RxIN1−
A1P
RxIN1+
A2M
RxIN2−
A2P
RxIN2+
CLK1M
RxCLKIN0−
CLK1P
RxCLKIN0+
A3M(valid for 8-bit LCD RxIN3−(valid for 8-bit LCD
only; no connect for 6-bit only; no connect for 6-bit
LCD)
LCD)
A3P(valid for 8-bit LCD RxIN3+(valid for 8-bit LCD
only; no connect for 6-bit only; no connect for 6-bit
LCD)
LCD)
A4M
No connect
A4P
No connect
A5M
No connect
A5P
No connect
A6M
No connect
A6P
No connect
A7M
No connect
A7P
No connect
CLK2M
No connect
CLK2P
No connect
3. To configure for single pixel or dual pixel application using
the DS90C387R with DS90CF388, the “DUAL” pin must be
set to Vcc (dual RGB) or Gnd (single RGB). Also, “BAL” pins
on both devices have to in the same logic state. For cable
length more than two meters, pre-emphasis feature is rec-
ommended.
4. In dual mode, DS90C387R has two LVDS clock outputs
enabling an interface to two FPD-Link ’notebook’ receivers
(DS90CF384/DS90CF386). “BAL” pin must be set to Gnd to
disable DC balance function for DS90CF384/DS90CF386
doesn’t support DC balance function. In single mode, out-
puts A4-to-A7 and CLK2 are disabled which reduces power
dissipation. For cable length more than two meters, pre-
emphasis feature is recommended.
The DS90CF388 is able to support single or dual pixel
interface up to 112MHz operating frequency. This receiver
may also be used to interface to a VGA controller with an
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