DS90C387R Datasheet, PDF (11/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R Pin Description—LDI
Transmitter
Pin Name
I/O
No.
Description
D0-D23
I
24
LVTTL level single-ended inputs or low swing pseduo differential inputs.
Reference to V_REF pin.
D0-D11 are for 12-bit input mode (24 RGB data); D0-D11 (first 12-bit port)
and D12-D23 (second 12-bit port) are for two 12-bit input mode (48 RGB
data).
DE
I
1
LVTTL level or low swing level inputs for data enable. This signal is HIGH
when input pixel data is valid to DS90C387R provided that R_FDE = HIGH.
HSYNC
I
1
Horizontal Sync input control signal. LVTTL level or low swing level.
VSYNC
I
1
Vertical Horizontal Sync input control signal. LVTTL level or low swing level.
AnP
O
8
Positive LVDS differential data output.
AnM
O
8
Negative LVDS differential data output.
CLKINP
I
1
In LVTTL level operation, this is a single-ended clock. In low swing
operation, this is the positive differential clock input .
CLKINM
I
1
In LVTTL level operation, no connect or connect to V_REF pin. Do not connect
to GND under any condition. In low swing operation, this is negative
differential clock input .
R_FB
I
1
LVTTL level input for selecting the Primary clock edge E1. Falling clock
edge selected when input is HIGH; Rising clock edge selected when input is
LOW.(Note 14)
R_FDE
I
1
LVTTL level input. Programmable control (DE) strobe select. Tie HIGH for
data active when DE is HIGH. (Note 14)
CLK1P
O
1
Positive LVDS differential clock output.
CLK1M
O
1
Negative LVDS differential clock output.
PD
I
1
LVCMOS level input. Input = LOW will place the entire device in power down
mode. Outputs of the device will be in TRI-STATE mode to ensure low
current at power down. (Note 14)
Input = HIGH for normal operation.
PLLSEL
I
1
LVTTL level in. Tie to Vcc for normal operation. (Note 14)
BAL
I
1
LVTTL level input. Mode select for dc balanced or non-dc balanced
interface. DC balance is active when input is high. (Note 14)
PRE
I
1
Pre-emphasis level select. Pre-emphasis is active when input is tied to V_CC
through external pull-up resistor. Resistor value determines pre-emphasis
level (see table in application section). For normal LVDS drive level
(minimum pre-emphasis) leave this pin open (do not tie to ground).(Note 14)
DUAL
I
1
LVTTL level input. Input = LOW for one 12-bit input mode, 24 RGB data in,
24 RGB data out.(Note 14)
LVTTL level input. Input = V_CC for two 12-bit input mode, 48 RGB data in,
48 RGB data out.(Note 14)
V_CC
I
1
Connect to power supply with voltage stated under ” Recommended
Operating Conitions ” on page 3. Power supply pin for LVTTL inputs and
digital circuitry, pin53.
GND
I
4
Ground pins for LVTTL inputs and digital circuitry, pins 9, 11, 52, 77.
I2V_CC
I
1
Connect to power supply with voltage stated under ” Recommended
Operating Conitions ” on page 3, pin 68.
V_CC3V
I
3
Connect to power supply with voltage stated under ” Recommended
Operating Conitions ” on page 3, pins 70, 79, 95.
GND_3V
SGND
I
3
Ground pin(s) for powering the data inputs, pins 71, 80, 96.
I
1
Connect to ground, pin 69.
11
www.national.com