DS90C387R Datasheet, PDF (25/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

Applications Information (Continued)
integrated LVDS transmitter without DC balance data trans-
mission. In this case, the receivers “BAL” pin must be tied
low (DC balance disabled).
Features Description:
1. Pre-emphasis: adds extra current during LVDS logic
transition to reduce the cable loading effects. Pre-emphasis
strength is set via a DC voltage level applied from min to max
(0.75V to Vcc) at the “PRE” pin. A higher input voltage on the
”PRE” pin increases the magnitude of dynamic current dur-
ing data transition. The “PRE” pin requires one pull-up resis-
tor (Rpre) to Vcc in order to set the DC level. There is an
internal resistor network, which cause a voltage drop. Please
refer to the tables below to set the voltage level.
TABLE 10. Pre-emphasis DC voltage level with (Rpre)
Rpre
1MΩ or NC
50kΩ
9kΩ
3kΩ
1kΩ
100Ω
Resulting PRE Voltage
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Effects
Standard LVDS
50% pre-emphasis
100% pre-emphasis
TABLE 11. Pre-emphasis needed per cable length
Frequency
85MHz
65MHz
PRE Voltage
1.5V
1.5V
Typical cable length
7 meters
10 meters
Note 23: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating
frequency.
2. DC Balance: In the balanced operating modes, in addition
to pixel and control information an additional bit is transmit-
ted on every LVDS data signal line during each cycle of
active data as shown in Figure 18. This bit is the DC balance
bit (DCBAL). The purpose of the DC Balance bit is to mini-
mize the short- and long-term DC bias on the signal lines.
This is achieved by selectively sending the pixel data either
unmodified or inverted.
The value of the DC balance bit is calculated from the
running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall
be calculated by subtracting the number of bits of value 0
from the number of bits value 1 in the current word. Initially,
the running word disparity may be any value between +7 and
−6. The running word disparity shall be calculated as a
continuous sum of all the modified data disparity values,
where the unmodified data disparity value is the calculated
data disparity minus 1 if the data is sent unmodified and 1
plus the inverse of the calculated data disparity if the data is
sent inverted. The value of the running word disparity shall
saturate at +7 and −6.
The value of the DC balance bit (DCBAL) shall be 0 when
the data is sent unmodified and 1 when the data is sent
inverted. To determine whether to send pixel data unmodi-
fied or inverted, the running word disparity and the current
data disparity are used. If the running word disparity is
positive and the current data disparity is positive, the pixel
data shall be sent inverted. If the running word disparity is
positive and the current data disparity is zero or negative, the
pixel data shall be sent unmodified. If the running word
disparity is negative and the current data disparity is positive,
the pixel data shall be sent unmodified. If the running word
disparity is negative and the current data disparity is zero or
negative, the pixel data shall be sent inverted. If the running
word disparity is zero, the pixel data shall be sent inverted.
Cable drive is enhanced with a user selectable pre-
emphasis feature that provides additional output current dur-
ing transitions to counteract cable loading effects. DC bal-
ancing on a cycle-to-cycle basis, is also provided to reduce
ISI (Inter-Symbol Interference). With pre-emphasis and DC
balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. These enhancements allow cables
5 to 10+ meters in length to be driven. Quality of the cable
can affect the length.
The data enable control signal (DE) is used in the DC
balanced mode to distinguish between pixel data and control
information being sent. It must be continuously available to
the device in order to correctly separate pixel data from
control information. For this reason, DE shall be sent on the
clock signals, LVDS CLK1 and CLK2, when operating in the
DC balanced mode. If the value of the control to be sent is 1
(active display), the value of the control word sent on the
clock signals shall be 1111000 or 1110000. If the value of the
control to be sent is 0 (blanking time), the value of the control
word sent on the clock signals shall be 1111100 or 1100000.
The control information, such as HSYNC and VSYNC, is
always sent unmodified. The value of the control word to
send is determined by the running word disparity and the
value of the control to be sent. If the running word disparity is
positive and the value of the control to be sent is 0, the
control word sent shall be 1110000. If the running word
disparity is zero or negative and the control word to be sent
is 0, the control word sent shall be 1111000. If the running
word disparity is positive and the value of the control to be
sent is 1, the control word sent shall be 1100000. If the
running word disparity is zero or negative and the value of
the control to be sent is 1, the control word sent shall be
1111100. The DC Balance bit shall be sent as 0 when send-
ing control information during blanking time. See Figure 19.
In backward compatible mode (BAL=low) control and data is
sent as regular LVDS data. See Figure 17.
Backwards Compatible Mode with FPD-Link
The transmitter provides a second LVDS output clock. Both
LVDS clocks will be identical in ’Dual pixel mode’. This
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