DS90C387R Datasheet, PDF (1/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

December 2003
DS90C387R
85MHz Dual 12-Bit Double Pumped Input LDI Transmitter
- VGA/UXGA
General Description
The DS90C387R transmitter is designed to support pixel
data transmission from a Host to a Flat Panel Display up to
UXGA resolution. It is designed to be compatible with Graph-
ics Memory Controller Hub( GMCH) by implementing two
data per clock and can be controlled by a two-wire serial
communication interface. Two input modes are supported:
one port of 12-bit( two data per clock) input for 24-bit RGB,
and two ports of 12-bit( two data per clock) input for dual
24-bit RGB( 48-bit total). In both modes, input data will be
clocked on both rising and falling edges in LVTTL level
operation, or clocked on the cross over of differential clock
signals in the low swing operation. Each input data width will
be 1/2 of clock cycle. With an input clock at 85MHz and input
data at 170Mbps, the maximum transmission rate of each
LVDS line is 595Mbps, for a aggregate throughput rate of
2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual
Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differ-
ential Signaling) data streams. DS90C387R can be pro-
grammed via the two-wire serial communication interface.
The LVDS output pin-out is identical to DS90C387. Thus,
this transmitter can be paired up with DS90CF388, receiver
of the 112MHz LDI chipset or FPD-Link Receivers in non-DC
Balance mode operation which provides GUI/LCD panel/
mother board vendors a wide choice of inter-operation with
LVDS based TFT panels.
DS90C387R also comes with features that can be found on
DS90C387. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC
Balancing on a cycle-to-cycle basis is also provided to re-
duce ISI( Inter-Symbol Interference), control signals (
VSYNC, HSYNC, DE) are sent during blanking intervals.
With pre-emphasis and DC Balancing, a low distortion eye-
pattern is provided at the receiver end of the cable. These
enhancements allow cables 5 to 15+ meters in length to be
driven depending on media characteristic and pixel clock
speed. Pre-emphasis is available in both the DC Balanced
and Non-DC Balanced modes. In the Non-DC Balanced
mode backward compatibility with FPD-Link Receivers is
obtained.
This chip is an ideal solution to solve EMI and cable size
problems for high-resolution flat panel display applications. It
provides a reliable industry standard interface based on
LVDS technology that delivers the bandwidth needed for
high-resolution panels while maximizing bit times, and keep-
ing clock rates low to reduce EMI and shielding require-
ments. For more details, please refer to the “Applications
Information” section of this datasheet.
Features
n Complies with Open LDI specification for digital display
interfaces
n 25 to 85MHz clock support
n Supports VGA through UXGA panel resolution
n Up to 4.76Gbps bandwidth in dual 24-bit RGB in-to-dual
pixel out application.
n Dual 12-bit Double Pumped Input DVO port.
n Pre-emphasis reduces cable loading effects.
n Drives long, low cost cables
n DC Balance data transmission provided by transmitter
reduces ISI distortion
n Transmitter rejects cycle-to-cycle jitter.(+/− 2ns of input
bit period)
n Support both LVTTL and low voltage level input(capable
of 1.0 to 1.8V)
n Two-wire serial communication interface up to 400 KHz
n Programmable input clock and control strobe select
n Backward compatible configuration with 112MHz LDI
and FPD-Link.
n Optional second LVDS clock for backward compatibility
w/ FPD-Link Receivers
n Compatible with TIA/EIA-644
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