DS90C387R Datasheet, PDF (23/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

LVDS Interface (Continued)
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FIGURE 19. Control Signals Transmitted During Blanking in DC-Balance mode
TABLE 9. Control Signals Transmitted During Blanking in DC-Balance mode
Control Signal
DE
HSYNC
VSYNC
Signal Level
HIGH
LOW
HIGH
LOW
HIGH
LOW
Channel
CLK1
A0
A1
Pattern
1111000 or 1110000
1111100 or 1100000
1100000 or 1111100
1110000 or 1111000
1100000 or 1111100
1110000 or 1111000
Note 22: The control signal during blanking shown above is for R_FDE=High, when R_FDE=Low, low/high patterns are reversed only for DE signal.
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