DS90C387R Datasheet, PDF (19/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

LVDS Interface (Continued)
TABLE 7. Two 12-bit (two data per clock) data mapping (DUAL=Vcc, BAL=Vcc/GND, A0-A7 are used). (Continued)
VGA - TFT Data Transmitter input pin names Receiver output pin names
TFT Panel Data
Signals Color Bits
Signals
B4
E1-D16
B22
B2
B4
B5
E1-D17
B23
B3
B5
B6
E1-D18
B24
B4
B6
MSB
B7
E1-D19
B25
B5
B7
FIGURE 16. How ds90c387r latch data
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Note 16: The lower half of the pixel is latched by the primary clock edge E1.
Note 17: Above figure only valids when R_FDE = HIGH, DE signal from GUI is active HIGH.
Note 18: D0 to D11 are clocked at the crossing point of CLKOUT+ and CLKOUT− when differential clock input is applied, DSEL = 0.
Note 19: Single-ended clock is not recommended for operation above 65MHz.
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