DS90C387R Datasheet, PDF (5/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Device driving the transmitter inputs
should comply to this table of recommendations.
Symbol
Parameter
Min
Typ
Max
Units
TCIT
TCIP
TCIH
TxCLK IN Transition Time (Figure 5)
TxCLK IN Period (Figure 6)
TxCLK in High Time (Figure 6)
DUAL = Gnd or V_CC
0.8
1.2
2.4
ns
DUAL = Gnd or V_CC
11.76
T
40
ns
0.4T
0.5T
0.6T
ns
TCIL
TxCLK in Low Time (Figure 6)
0.4T
0.5T
0.6T
ns
VDDQ
Low Swing Voltage Amplitude from GMCH
1.0
1.8
V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(Note 2)
Symbol
Parameter
Min
Typ
LLHT
LVDS Low-to-High Transition Time (Figure 4), PRE = no connect
0.14
(minimum pre-empahsis).
LVDS Low-to-High Transition Time (Figure 4), PRE = V_CC (max.
0.11
pre-empahsis).
LHLT
LVDS High-to-Low Transition Time (Figure 4), PRE = no connect
0.16
(mini. pre-empahsis).
LVDS High-to-Low Transition Time (Figure 4), PRE = V_CC (max.
0.11
pre-empahsis).
TCCS
TxOUT Channel to Channel Skew
100
TPPOS0 Transmitter Output Pulse Position for Bit0 f = 85MHz (Note 8) -300
0
from TxCLKout rising edge.
TPPOS1 Transmitter Output Pulse Position for Bit1
from TxCLKout rising edge.
1.38
1.68
TPPOS2 Transmitter Output Pulse Position for Bit2
from TxCLKout rising edge.
3.06
3.36
TPPOS3 Transmitter Output Pulse Position for Bit3
from TxCLKout rising edge.
4.74
5.04
TPPOS4 Transmitter Output Pulse Position for Bit4
from TxCLKout rising edge.
6.42
6.72
TPPOS5 Transmitter Output Pulse Position for Bit5
from TxCLKout rising edge.
8.10
8.40
TPPOS6 Transmitter Output Pulse Position for Bit6
from TxCLKout rising edge.
9.78
10.08
TSTC
TxIN Setup to TxCLK IN in low swing mode at 85 MHz (Figure 7)
1.8
THTC
TxIN Hold to TxCLK IN in low swing mode at 85 MHz (Figure 7)
2
TJCC
Transmitter Jitter Cycle-to-cycle (Figures f = 85 MHz
110
12, 13) (Note 5), DUAL = Gnd, V_CC = 3V _{f = 65 MHz}
80
f = 32.5 MHz
75
TPLLS Transmitter Phase Lock Loop Set (Figure 8)
TPDD
Transmitter Powerdown Delay (Figure 9)
TPDL
Transmitter Input to Output Latency (Figure f = 32.5/65/85 MHz
10)
(Note 9)
1.5TCIP
+4.1
Max
0.9
0.7
0.9
0.7
+300
1.98
3.66
5.34
7.02
8.70
10.38
150
120
115
10
100
Units
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ms
ns
ns
5
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