DS90C387R Datasheet, PDF (10/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 12) + ISI (Inter-symbol interference) (Note 13)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 12: Cycle-to-cycle jitter is less than 150 ps at 85 MHz
Note 13: ISI is dependent on interconnect length; may be zero
FIGURE 11. Receiver Skew Margin
10128825
FIGURE 12. TJCC Test Setup - DS90C387R
10128827
www.national.com
FIGURE 13. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter
10
10128828