DS90C387R Datasheet, PDF (17/28 Pages) National Semiconductor (TI) – 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

Two-Wire Serial Communication
Interface for Slave (Continued)
The master must generate a “ Start ”, by sending the 7-bit
slave address plus a 0 and wait for acknowledge from
DS90C387R. When DS90C387R acknowledges (the 1st
LVDS Interface
ACK) that the master is calling, the master then sends the
data register address byte and waits for acknowledge from
the slave. When the slave acknowledges (the 2nd ACK), the
master sends the data byte and wait for acknowledge from
the slave. When the slave acknowledges (the 3rd ACK), the
master generates a “ Stop ”. This completes the “ WRITE ”.
X
X=R
X=G
X=B
TABLE 5. LVDS data bit naming convention
Y
Z
Y=1
Y=2
Z=0-7
Description
Red
Green
Blue
Odd (First) Pixel
Even (Second) Pixel
LVDS bit number (not VGA controller LSB to MSB)
Note 15: For a 48-bit dual pixel application - LSB (Less Significant Bit) = R16,G16,B16,R26,G26,B26 and MSB (Most Significant Bit) = R15,G15,B15,R25,G25,B25.
TABLE 6. 12-bit (two data per clock) data mapping (DUAL=GND, BAL=Vcc/GND, only A0-A3 are used).
VGA - TFT Data
Signals Color Bits
24-bit
LSB
R0
R1
R2
R3
R4
R5
R6
MSB
R7
LSB
G0
G1
G2
G3
G4
G5
G6
MSB
G7
LSB
B0
B1
B2
B3
B4
B5
B6
MSB
B7
Transmitter input pin names
DS90C387R
E2-D4
E2-D5
E2-D6
E2-D7
E2-D8
E2-D9
E2-D10
E2-D11
E1-D8
E1-D9
E1-D10
E1-D11
E2-D0
E2-D1
E2-D2
E2-D3
E1-D0
E1-D1
E1-D2
E1-D3
E1-D4
E1-D5
E1-D6
E1-D7
Receiver output pin names
DS90CF388
R16
R17
R10
R11
R12
R13
R14
R15
G16
G17
G10
G11
G12
G13
G14
G15
B16
B17
B10
B11
B12
B13
B14
B15
TFT Panel Data
Signals
18-bit
24-bit
R0
R1
R0
R2
R1
R3
R2
R4
R3
R5
R4
R6
R5
R7
G0
G1
G0
G2
G1
G3
G2
G4
G3
G5
G4
G6
G5
G7
B0
B1
B0
B2
B1
B3
B2
B4
B3
B5
B4
B6
B5
B7
17
www.national.com