HPC46100 Datasheet, PDF (5/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

40 MHz (Continued)
AC Electrical Characteristics (Continued)
See Notes 1 and 4 and Figure 1 thru Figure 5 V_CC e 5 0V g10% unless otherwise specified T_A e 25 C one wait state
Symbol
Parameter
Min
Max
Units
E SIGNAL TIMING PARAMETERS
t_RWSE e 0 25 t_C b 7
WR Falling Edge to E Rising Edge
55
ns
t_RWHE e 0 5 t_C b 7
E Falling Edge to WR Rising Edge
18
ns
t_ASE e t_C b 20
Address Valid to E Rising Edge
30
ns
t_RDE e WS b 20
E Falling Edge to Data Input Valid
30
ns
SLOW PERIPHERAL TIMING PARAMETERS
t_PLL e t_C b 5
PALE Pulse Width
45
ns
t_PST e 0 75 t_C b 10
Address Valid to PALE Falling Edge
27 5
ns
t_PVL e 0 75 t_C b 15
Address Hold from PALE Falling Edge
22 5
ns
t_PVP e 0 75 t_C b 10
PALE Falling Edge to RD or WR Falling Edge
27 5
ns
t_PCSA e 0 25 t_C b 12 5
Chip Select Setup to PALE Falling Edge
0
ns
t_PAS e 1 5 t_C b 20
Address Setup to RD or WR Falling Edge
55
ns
t_PCSS e t_C b 15
Chip Select Setup to RD or WR Falling Edge
35
ns
t_PCSH e 0 5 t_C b 15
Chip Select Hold from RD or WR Rising Edge
10
ns
t_PACC e 5 t_C b 25
Address Valid to Input Data Valid
225
ns
t_PRD e 3 5 t_C b 25
RD Falling Edge to Data In Valid
150
ns
t_PDR e t_C (max)
Data Hold after RD Rising Edge
0
50
ns
t_PRW e 3 5 t_C b 15
RD Strobe Width
160
ns
t_PSW e 3 0 t_C b 20
Data Setup before WR Rising Edge
130
ns
t_PHW e t_C b 20
Data Hold after WR Rising Edge
30
ns
t_PWW e 3 5 t_C b 15
WR Strobe Width
160
ns
Note C_L e 40 pF
Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t_CKIR and t_CKIL) on CKI input less than 2 5 ns
Note 2 Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3 t_HAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle begin executed If HLD falling
edge occurs later t_HAE as long as (3 t_C a 4 WS a 72 t_C a 100) may occur depending on the following CPU instruction cycles its wait states and ready input
Note 4 WS (t_WAIT) x (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency t_C e 40 MHz with
one wait state programmed
Note 5 Due to testing limitations actual limits will be better
5