HPC46100 Datasheet, PDF(16/32 Page) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

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HPC46100 Datasheet, PDF (16/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

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Power Save Modes (Continued)

including the clock and timers are stopped when the HALT

mode is entered with the NMI input high When the HALT

mode is entered with the NMI input low the high speed

timers (T4 T5 and T6) remain active In the HALT mode

power requirements for the HPC46100 are minimal and the

applied voltage (VCC) may be decreased without altering the

state of the machine There are two ways of exiting the

HALT mode via the RESET or the NMI The RESET input

re-initializes the processor Use of the NMI input will gener-

ate a vectored interrupt and resume operation from that

point with no initialization The HALT mode can be enabled

or disabled by means of a control register HALT enable To

prevent accidental use of the HALT mode the HALT enable

IDLE MODE

THE HPC46100 is placed in the IDLE mode through the

PSW In this mode all processor activity except the internal

oscillator the high speed timers (T4 T5 and T6) and Timer

T0 is stopped As with the HALT mode the processor is

returned to full operation by the RESET or NMI inputs but

without waiting for oscillator stabilization A timer T0 over-

flow will also cause the HPC46100 to resume normal opera-

tion

HPC46100 Interrupts

Complex interrupt handling is easily accomplished by the

HPC46100âs vectored interrupt scheme There are eight

possible interrupt sources as shown in Table I

TABLE I Interrupts

Vector

Address

Interrupt Source

Arbitration

Ranking

FFFF FFFE RESET

FFFD FFFC Non-maskable external on

rising edge of I1 pin

FFFB FFFA External interrupt on I2 pin

FFF9 FFF8 External interrupt on I3 pin

FFF7 FFF6 External interrupt on I4 pin

FFF5 FFF4 Overflow on internal timers

FFF3 FFF2 Internal by UART or

external on EI pin

FFFF1 FFF0 A D converter

INTERRUPT ARBITRATION

The HPC46100 contains arbitration logic to determine which

interrupt will be serviced first if two or more interrupts occur

simultaneously The arbitration ranking is given in Table I

The interrupt on RESET has the highest rank and is serv-

iced first

INTERRUPT PROCESSING

Interrupts are serviced after the current instruction is com-

pleted and except for the RESET which is serviced immedi-

ately RESET and EI are level-LOW-sensitive interrupts All

other external interrupts are edge-sensitive NMI is positive-

edge sensitive The external interrupts on I2 I3 and I4 can

be software selected to be rising or falling edge

INTERRUPT CONTROL REGISTERS

The HPC46100 allows the various interrupt sources and

conditions to be programmed This is done through the vari-

ous control registers A brief description of the different con-

trol registers is given below

INTERRUPT ENABLE REGISTER (ENIR)

RESET and the External Interrupt on I1 are non-maskable

interrupts The other interrupts can be individually enabled

or disabled Additionally a Global Interrupt Enable Bit in the

ENIR Register allows the Maskable interrupts to be collec-

tively enabled or disabled Thus in order for a particular

interrupt to request service both the individual enable bit

and the Global Interrupt bit (GIE) have to be set

INTERRUPT PENDING REGISTER (IRPD)

The IRPD register contains a bit allocated for each interrupt

vector excluding the EI interrupt which has a dedicated reg-

ister containing an interrupt enable and pending bit The

occurance of specified interrupt trigger conditions causes

the appropriate bit to be set There is no indication of the

order in which the interrupts have been received The bits

are set independently of the fact that the interrupts may be

disabled IRPD is a Read Write register The bits corre-

sponding to the maskable external interrupts are normally

cleared by the HPC46100 after servicing the interrupts For

the interrupts from the on-board peripherals the user has

the responsibility of resetting the interrupt pending flags

through software The NMI bit is read only and I2 I3 and I4

are designed as to only allow a zero to be written to the

pending bit (writing a one has no effect) A LOAD IMMEDI-

ATE instruction is to be the only instruction used to clear a

bit or bits in the IRPD register This allows a mask to be

used thus ensuring that the other pending bits are not af-

fected

INTERRUPT CONDITION REGISTER (IRCD)

Three bits of the register select the input polarity of the

external interrupt on I2 I3 and I4

EI INTERRUPT CONFIGURATION REGISTER (EICON)

The EI pin is an active low level sensitive interrupt Inter-

rupts from the EI pin are enabled by using the EICON regis-

ter

SERVICING THE INTERRUPTS

The Interrupt once acknowledged pushes the program

counter (PC) onto the stack then incrementing the stack

pointer (SP) by two The Global Interrupt Enable bit (GIE) is

copied into the CGIE bit of the PSW register it is then reset

thus disabling further interrupts The program counter is

loaded with the contents of the memory at the vector ad-

dress and the processor resumes operation at this point At

the end of the interrupt service routine the user does a

RETI instruction to pop the stack and re-enable interrupts if

the CGIE bit is set or RET to just pop the stack if the CGIE

bit is clear and then returns to the main program The GIE

bit can be set in the interrupt service routine to nest inter-

rupts if desired Figure 15 shows the interrupt enable logic

RESET

RESET is an active-low Schmitt trigger input that initializes

the processor and sets all pins in a TRI-STATE condition

except for CK0 CKI ST1 ST2 HBE and WO when held

low When rising edge is detected on RESET the processor

vectors to FFFF FFFE and resumes operation at the ad-

dress contained at that memory location

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