HPC46100 Datasheet, PDF (25/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

A D Converter (Continued)
Source impedances greater than 1 kX on the analog input
lines will adversely affect internal RC charging time during
input sampling As shown in Figure 28 the analog switch to
the DAC array is closed only during the 2 A D cycle sample
time Large source impedances on the analog inputs may
result in the DAC array not being charged to the correct
voltage levels causing scale errors
If large source resistance is necessary the recommended
solution is to slow down the A D clock speed in proportion
to the source resistance The A D converter may be operat-
ed at the maximum speed for R_S less than 1 kX For R_S
greater than 1 kX A D clock speed needs to be reduced
For example with R_S e 2 kX the A D converter may be
operated at half the maximum speed A D converter clock
speed may be slowed down by either increasing the A D
prescaler divide-by or decreasing the CKI clock frequency
The A D clock speed may be reduced to its minimum fre-
quency of 100 kHz
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data It is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block (see Figure 29 )
The HPC46100 supports shared memory access with two
pins The pins are the RDY HLD input pin and the HLDA
output pin The user can software select either the Hold or
Ready function by the state of a control bit The HLDA out-
put is multiplexed onto port B
The host uses DMA to interface with the HPC46100 The
host initiates a data transfer by activating the HLD input of
the HPC46100 In response the HPC46100 places its sys-
tem bus in a TRI-STATE Mode freeing it for use by the host
FIGURE 29 Shared Memory Application Using HOLD
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