HPC46100 Datasheet, PDF (24/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

A D Converter (Continued)
TABLE II Operating Modes
Mode 0
single-ended single channel single result
register one-shot (default value on power-
up)
Mode 1
single-ended single channel single result
register continuous
Mode 2
single-ended single channel multiple result
registers stop after 8
Mode 3
single-ended multiple channel multiple
result register continuous
Mode 4
differential single channel-pair single result
register-pair one-shot
Mode 5
differential single channel-pair single result
register-pair continuous
Mode 6
differential single channel-pair multiple
result register-pairs stop after 4 pairs
Mode 7
differential multiple channel-pair multiple
result register-pairs continuous
Mode 8
single-ended single channel single result
register one-shot (default value on power-
up) quiet address data bus
Mode C
differential single channel-pair single result
register-pair one-shot quiet address data
bus
The same operating modes for single-ended operation also
apply when the inputs are taken from channel-pairs in differ-
ential mode The programmer can configure the A D to con-
vert on any selected channel-pair and store the result in its
associated result register-pair then stop The A D can also
be programmed to do this continuously Conversion can
also be done on any channel-pair storing the result into four
result register-pairs for a history of the differential input Fi-
nally all input channel-pairs can be converted continuously
The final mode of operation suppresses the external ad-
dress data bus activity during the single conversion modes
These quiet modes of operation utilize the RDY function of
the HPC Core to insert wait states in the instruction being
executed in order to limit digital noise in the environment
due to external bus activity when addressing external mem-
ory
CONTROL
The conversion clock supplied to the A D converter can be
selected by three bits in ADCR1 These bits are used as a
prescaler on CKI and can provide a clock rate from CKI 4
to CKI 32 These bits can be used to ensure that the A D is
clocked as fast as possible when different external crystal
frequencies are used Controlling the starting of conversion
cycles in each of the operating modes can be done by four
different methods The method is selected by two bits called
SC (ADCR3 0 – 1) Conversion cycles can be initiated
through software by resetting a bit in a control register
through hardware by an underflow of Timer T2 or externally
by a rising or falling edge of a signal input on I7
INTERRUPTS
The A D converter can interrupt the HPC when it completes
a conversion cycle if one of the non-continuous modes has
been selected If one of the cycle modes was selected then
the converter will request an interrupt after eight conver-
sions If one of the one-shot modes was selected then the
converter will request an interrupt after every conversion
When this interrupt is generated the HPC vectors to the
A D converter interrupt vector location at address FFF0
Analog Input and Source Resistance Considerations
Figure 28 shows the A D pin model for the HPC46100 in
single ended mode The differential mode has similiar A D
pin model The leads to the analog inputs should be kept as
short as possible Both noise and digital clock coupling to
an A D input can cause conversion errors The clock lead
should be kept away from the analog input line to reduce
coupling The A D channel input pins do not have any inter-
nal output driver circuitry connected to them because this
circuitry would load the analog input signals due to output
buffer leakage current
The analog switch is closed only during the sample time
FIGURE 28 Port D Input Structure
TL DD 11289 – 34
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