HPC46100 Datasheet, PDF (14/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

I O Ports (Continued)
PORT I
Port I is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following func-
tions
Pin Alternate
Function
I0 R5B
Timer T5 R5B Input
I1 NMI
Nonmaskable Interrupt Input
I2 INT2
Maskable Interrupt Input Capture
I3 INT3
Maskable Interrupt Input Capture
I4 INT4
Maskable Interrupt Input Capture
I5 SI
MICROWIRE PLUS Data Input
I6 RDX
UART Data Input
I7 R6B
Timer T6 R6B Input and A D Trigger Input
PORT D
Port D is an 8-bit input port that can be used as general
purpose digital inputs and as analog inputs for the A D con-
verter
PORT P
Port P is a 3-bit input output port that is used as general
purpose outputs or I O that is controlled by timers T4 T5
and T6 These pins can be configured as Pulse Width Modu-
lated Outputs (PWM) capture inputs or event counter in-
puts
POWER SUPPLY PINS
Four pairs of power supply pins are provided to minimize
cross talk between the analog digital and output driver sec-
tions of the chip
Pin
V_CC
GND
DV_CC
DGND
AV_CC
AV_SS
V_REF
AGND
Function
Power for Digital Logic
Ground for Digital Logic
Power for Output Drivers
Ground for Output Drivers
Power for Analog Logic
Ground for Analog Logic
A D Converter Reference Voltage Input
Ground Reference for Analog Logic
CLOCK PINS
Pin
Function
CKI
System Oscillator Input External Clock Input
CKO
System Oscillator Output (Inversion of CKI)
CK2
Clock Output (CKI divided by 2)
OTHER PINS
Pin
RESET
PALE
RDY HLD
WO
ST1
ST2
EXM
EI
Function
System reset input active low
Slow peripheral address latch enable
Has two uses selected by a software bit
It’s either a READY input to extend the
bus cycle for slower memories or HOLD
request input to put the bus in a high
impedance state for DMA purposes
This is an active low open drain output
that signals an illegal situation has been
detected by the WATCHDOG logic
Bus Cycle Status Output indicates first
opcode fetch
Bus Cycle Status Output indicates
machine states (skip interrupt and first
instruction cycle)
External memory enable (active high)
disables internal ROM and maps it to
external memory
Has two uses it’s either an active low
level external interrupt with vector
address FFF3 FFF2 which is shared with
the UART or Timer T4 R4B input
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