HPC46100 Datasheet, PDF (15/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

Connection Diagram
Operating Modes
The HPC46100 does not have any internal ROM and has
only one mode of operation the Expanded ROMless Mode
The EXM pin must be pulled high (logic ‘‘1’’) The EA bit in
the PSW register of the HPC46100 is hard wired to a logic
‘‘1’’ The use of this bit is reserved Currently the
HPC46100 is intended for use with external memory The
external memory may be any combination of ROM RAM or
peripherals and may be configured with an 8-bit or 16-bit
external address data bus (see Figure 16 and Figure 17 )
Up to 62k bytes of external memory may be accessed
Wait States
The HPC46100 provides four selectable Wait States that
allow access to slower memories The Wait States are se-
lectable by the state of two bits in the PSW register or by
TL DD 11289 – 17
two bits in the Chip Select Control registers Additionally
the RDY input may be used to extend the instruction or
memory access cycle allowing the user to interface with
slow memories and peripherals There also is a slow periph-
eral bus mode when using the Chip Select logic
Power Save Modes
Two power saving modes are available on the HPC46100
HALT and IDLE In the HALT mode all processor activities
are stopped In the IDLE mode the internal oscillator and
timer T0 are active but all other processor activities are
stopped In either mode all internal RAM registers and I O
are unaffected
HALT MODE
The HPC46100 is placed in the HALT mode under software
control by setting bits in the PSW All processor activities
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