HPC46100 Datasheet, PDF (23/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

HPC46100 UART (Continued)
TL DD 11289 – 29
FIGURE 27 UART Block Diagram
The Baud Rate Generator is controlled by the register pair
PSR and BAUD The Prescaler factor is selected by the
upper 5 bits of the PSR register (the PRESCALE field) in
units of the CK2 clock from 1 to 16 in step increments
The lower 3 bits of the PSR register in conjunction with the
8 bits of the baud register form the 11-bit BAUDRATE field
which defines a baud rate divisor ranging from 1 to 2048 in
units of the prescaled clock selected by the PRESCALE
field
In Asynchronous Mode the resulting baud rate is of the
clocking rate selected through the BRG circuit The maxi-
mum baud rate generated using the BRG is 625 kbaud
In the Synchronous Mode data is transmitted on the rising
edge and received on the falling edge of the external clock
Although the data is transmitted and received synchronous-
ly it is still contained within an asynchronous frame i e a
start bit parity bit (if selected) and stop bit(s) are still pres-
ent
UART ATTENTION MODE
The HPC46100 UART features an Attention Mode of opera-
tion This mode of operation enables the HPC46100 to be
networked with other processors Typically in such environ-
ments the messages consist of addresses and actual data
Addresses are specified by having the ninth bit in the data
frame set to 1 Data in the message is specified by having
the ninth bit in the data frame reset to 0 The UART moni-
tors the communication stream looking for addresses
When the data word with the ninth bit set is received the
UART signals the HPC46100 with an interrupt The proces-
sor then examines the content of the receiver buffer to de-
cide whether it has been addressed and whether to accept
subsequent data
A D Converter
The HPC46100 has an on-board eight-channel 8-bit Analog
to Digital converter Conversion is performed using a suc-
cessive approximation technique The A D converter cell
can operate in single-ended mode where the input voltage
is applied across one of the eight input channels (D0 – D7)
and AGND or in differential mode where the input voltage is
applied across two adjacent input channels The A D con-
verter will convert up to eight channels in single-ended
mode and up to four channel-pairs in differential mode
OPERATING MODES
The operating modes of the converter are selected by 4 bits
called ADMODE (ADCR2 4 – 7) see Table II Associated with
the eight input channels in single-ended mode are eight re-
sult registers one for each channel The A D converter can
be programmed by software to convert on any specific
channel storing the result in the result register associated
with that channel It can also be programmed to stop after
one conversion or to convert continuously If a brief history
of the signal on any specific input channel is required the
converter can be programmed to convert on that channel
and store the consecutive results in each of the result regis-
ters before stopping As a final configuration in single-ended
mode the converter can be programmed to convert the sig-
nal on each input channel and store the result in its associ-
ated result register continuously
Associated with each even-odd pair of input channels in
differential mode of operation are four result register-pairs
The A D converter performs two conversions on the select-
ed pair of input channels One conversion is performed as-
suming the positive connection is made to the even channel
and the negative connection is made to the following odd
channel This result is stored in the result register associat-
ed with the even channel Another conversion is performed
assuming the positive connection is made to the odd chan-
nel and the negative connection is made to the preceding
even channel This result is stored in the result register as-
sociated with the odd channel This technique does not re-
quire that the programmer know the polarity of the input
signal If the even channel result register is non-zero (mean-
ing the odd channel result register is zero) then the input
signal is positive with respect to the odd channel If the odd
channel result register is non-zero (meaning the even chan-
nel result register is zero) then the input signal is positive
with respect to the even channel
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