HPC46100 Datasheet, PDF (20/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

Timer Overview (Continued)
CORE TIMERS
Timer T0 is a free-running timer counting up at a fixed
CKI 16 (Clock Input 16) rate It is used for Watchdog logic
high speed event capture and to exit from the IDLE mode
Consequently it cannot be stopped or written to under soft-
ware control Timer T0 permits precise measurements by
means of the capture registers I2CR I3CR and I4CR Reg-
isters I2CR and I3CR have the alternate function of being
R1 and T1 respectively The function of these registers
(I2CR R1 and I3CR T1) are mutually exclusive and under
the control of software The capture registers I2CR I3CR
and I4CR respectively record the value of timer T0 when
specific events occur on the interrupt pins I2 I3 and I4 The
control register IRCD programs the capture registers to trig-
ger on either a rising edge or a falling edge of its respective
input The specified edge can also be programmed to gen-
erate an interrupt
The timers T2 and T3 have a clock rate which is selectable
The clock input to these two timers may be selected from
the following two sources an external pin or derived inter-
nally by dividing the clock input Timer T2 has additional
capability of being clocked by the timer T3 underflow This
allows the user to cascade timers T3 and T2 into a 32-bit
timer counter
The timers T1 through T3 in conjunction with their registers
form Timer-Register pairs All the Timer-Register pairs can
be read from or written to Each timer can be started or
stopped under software control Once enabled the timers
count down and upon underflow the contents of its associ-
ated register are automatically loaded into the timer
Synchronous Outputs
There are four synchronous timer outputs (TS0 through
TS3) that work in conjunction with the timer T2 The syn-
chronous timer outputs can be used either as regular out-
puts or individually programmed to toggle on timer T2 un-
derflow
Note These outputs are shared with the chip select outputs The use of
these two functions are mutually exclusive
TIMERS T4 T5 AND T6
The HPC46100 has a set of three powerful timers counters
T4 T5 and T6 Since the three timers T4 T5 and T6 are
identical all comments are equally applicable to any of the
three timer blocks
These timers are designed to allow the device to easily per-
form all timer functions with minimal software overhead All
timers are synchronized on the first overflow of timer T0
Each timer has four 16-bit registers dedicated to it a control
register (TnCON) timer register (Tn) and two auto-load
capture registers (RnA RnB) Figure 21 shows a block dia-
gram of the three high speed timers
TL DD 11289 – 23
FIGURE 21 High Speed Timers Block
TIMER CONTROL REGISTERS
There are three timer control registers (T4CON T5CON and
T6CON) These control registers have bits which set the
clock input rate mode of operation and interrupt control
structure Each timer control register has interrupt pending
and interrupt acknowledge bits for Tn RnA and RnB and a
global interrupt pending bit for that specific timer There are
bits to enable disable the interrupts from Tn RnA and RnB
The clock input rate can be selected to be CKI 2 CKI 4
CKI 8 or CKI 16 The Four modes of operation are Exter-
nal Event Counter mode Input Capture mode Processor
Independent PWM mode and externally triggered PWM
mode
MODE 0 EXTERNAL EVENT COUNTER MODE
This mode is the default after RESET In this mode the timer
register Tn is decremented each time there is an active
edge on the A input The active edge is determined by the
value of a bit in the control register Upon every underflow of
the timer register (Tn) the timer (Tn) is aternately reloaded
with the contents of the supporting registers RnA and RnB
The first underflow of the timer after entry into this mode will
cause the timer to reload from register RnA All following
underflows will alternate which reload is used beginning with
RnB Every underflow from the timer will set a Tn global
interrupt pending bit in the control register The selected
edge on Input A and Input B will also set corresponding
pending bits in the control register Figure 22 shows a block
diagram of the high speed timers in Mode 0
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