HPC46100 Datasheet, PDF (1/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

PRELIMINARY
June 1994
HPC46100 High-Performance microController
with DSP Capability
General Description
The HPC46100 is a member of the HPC^TM family of High
Performance microControllers Each member of the family
has a similar core CPU with unique memory resources and
I O configuration to suit specific applications The
HPC46100 is fabricated in National’s advanced microCMOS
technology This process combined with an advanced archi-
tecture provides fast flexible I O control efficient data ma-
nipulation high speed computation and low power con-
sumption
Throughput is enhanced by operating the HPC46100 at fre-
quencies up to 40 MHz by integrating a Multiply Accumu-
late Unit (MAU) onto the chip and by optimizing instructions
to increase efficiency These features increase performance
in closed loop digital servo and filter applications
The HPC devices are complete microcomputers on a single
chip All system timing internal logic RAM and I O are
provided on the chip to produce a cost effective solution
for high performance applications On-chip functions
such as an MAU unit PWM outputs Chip Select Signals
UART up to seven 16-bit timers with input capture
capability WATCHDOG^TM logic vectored interrupts and
MICROWIRE PLUS^TM provide a high level of system inte-
gration The ability to directly address up to 64 kbytes of
memory enables the HPC to be used in powerful applica-
tions typically performed by microprocessors and peripheral
chips
(Continued)
Features
Y _{Multiply Accumulate Unit for fast signed multiply or mul-}
tiply-accumulate
Y _{High speed 16 bit timers with PWM outputs or input}
capture logic
Y _{4 Chip select output logic with programmable control}
Y _{8-channel 8-bit A D Converter}
Y _{1024 bytes of on-chip 0 wait state RAM}
Y _{FAST 100 ns for fastest instruction when using}
40 0 MHz clock
Y _{Very low power with two power save modes IDLE and}
HALT
Y _{UART full duplex with a programmable baud rate gen-}
erator and parity checking detection
Y _{MICROWIRE PLUS serial I O interface}
Y _{8 vectored interrupt sources}
Y _{Signed overflow flag for add and subtract instructions}
Y _{16 x 16 multiply and 32 x 16 divide}
Y _{16-bit architecture with byte and word operations}
Y _{64 kbytes of direct memory addressing}
Y _{8- or 16-bit wide external memory}
Y _{Program instructions can be executed from RAM}
Y _{Up to 31 general purpose I O lines that are memory}
mapped
Y _{WATCHDOG logic}
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
HPCTM WATCHDOGTM MICROWIRE PLUSTM and MICROWIRETM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL DD11289
TL DD 11289 – 1
RRD-B30M105 Printed in U S A