HPC46100 Datasheet, PDF (21/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

Timer Overview (Continued)
MODE 2 PROCESSOR INDEPENDENT PWM MODE
As the name suggests this mode allows the device to gen-
erate a PWM signal with very minimal user intervention The
user only has to define the parameters of the PWM signal
(ON time and OFF time) Once begun the timer block will
continuously generate the PWM signal completely indepen-
dent of the microcontroller The user software services the
timer block only when the PWM parameters require updat-
ing In this mode the timer Tn counts down at a fixed rate as
programmed in the control register Upon every underflow
the timer is alternately reloaded with the contents of its sup-
porting registers RnA and RnB The very first underflow of
the timer after entry into this mode causes the timer to re-
load from the register RnA Subsequent underflows cause
the timer to be reloaded from the registers alternately begin-
ning with the register RnB Figure 24 shows a block diagram
of the timer in PWM mode
TL DD 11289 – 24
FIGURE 22 External Event Counter
MODE 1 DUAL INPUT CAPTURE MODE
The device can precisely measure external frequencies or
time external events by placing the timer in the input capture
mode In this mode the timer Tn is constantly running at a
fixed rate as selected in the timer control register The two
registers RnA and RnB act as capture registers Each reg-
ister is loaded with the contents of the timer register Tn
when an active edge on it’s associated pin is detected The
active edge is determined by the value of two bits in the
control register The active edge for each input pin can be
specified independently and can be programmed to gener-
ate an interrupt The interrupt can be generated on an input
from the A or B input along with an underflow of the timer
register (Tn) Figure 23 shows a block diagram of the timer
in Input Capture mode
TL DD 11289 – 25
FIGURE 23 Dual Input Capture
FIGURE 24 PWM
TL DD 11289 – 26
The underflow can be programmed to toggle the A output
pin (Port P) The underflow can also be programmed to gen-
erate interrupts These interrupts can occur on a reload
from RnA or RnB This gives the user the flexibility of inter-
rupting once per PWM period on either the rising or falling
edge of the PWM output Alternatively the user may choose
to interrupt on both edges of the PWM output
MODE 3 EXTERNALLY TRIGGERED
PWM PORT OUTPUT
In this mode the timer is stopped and the corresponding
port P pin can be programmed as a general purpose output
pin The timer block can be programmed to remain halted
using its A pin for use as a general purpose output or it can
be programmed to exit mode 3 and enter mode 2 (Proces-
sor Independent PWM) when a rising edge is detected on
the B input
The external triggering of this feature provides the capability
of generating a delayed pulse triggered by an external event
as follows From the rising edge of the B input the timer
enters PWM mode When the timer register underflows the
output toggles and the value of RnA is loaded to the timer
The next underflow will cause the RnB register to load into
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