HPC46100 Datasheet, PDF (4/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

40 MHz (Continued)
AC Electrical Characteristics (Continued)
See Notes 1 and 4 and Figure 1 thru Figure 5 ) V_CC e 5 0V g10% unless otherwise specified T_A e 25 C one wait state
Symbol
Parameter
Min
Max
Units
EXTERNAL HOLD
t_SALE e 0 75 t_C a 40
t_HWP e 0 75 t_C a 35
t_HAE e 0 75 t_C a 100
t_HAD e 0 75 t_C a 85
t_BF
t_BE e 0 75 t_C a 30
HLD Falling Edge before ALE Rising Edge
77 5
ns
HLD Pulse Width
72 5
ns
HLDA Falling Edge after HLD Falling Edge (Note 3)
137 5
ns
HLDA Rising Edge after HLD Rising Edge
122 5
ns
Bus TRI-Stated after HLDA Falling Edge (Note 5)
70
ns
Bus Enable after HLDA Rising Edge
67 5
ns
NATIVE BUS TIMING ADDRESS CYCLE
t_LL e 0 5 t_C b10
t_1ALR
t_1ALF
t_2ALR e 0 25 t_C a 20
t_2ALF e 0 25 t_C a 20
t_ST e 0 25 t_C b 9
t_VP e 0 5 t_C b 10
READ CYCLE
ALE Pulse Width
15
ns
ALE Rising Edge after CK1 Rising Edge (Note 2)
0
35
ns
ALE Falling Edge after CK1 Falling Edge (Note 2)
0
35
ns
ALE Rising Edge after CK2 Rising Edge
32 5
ns
ALE Falling Edge after CK2 Falling Edge
32 5
ns
Address Valid to ALE Falling Edge
35
ns
Address Hold after ALE Falling Edge
15
ns
t_RW e 0 25 t_C a WS b 15
t_ARD e 0 75 t_C b 20
t_ARR e 0 5 t_C b 20
t_RD e 0 25 t_C a WS b 20
t_DR
t_ACC e t_C a WS b 20
WRITE CYCLE
RD Pulse Width
Address Valid to RD Falling Edge
ALE Falling Edge to RD Falling Edge
RD Falling Edge to Input Data Valid
Data Hold after RD Rising Edge
Address Valid to Input Data Valid
47 5
ns
17 5
ns
5
ns
42 5
ns
0
50
ns
80
ns
t_WW e 0 75 t_C a WS b 15
t_V e 0 5 t_C a WS b 20
t_HW e 0 5 t_C b 10
t_AWR e 0 75 t_C b 20
READY INPUT
WR Pulse Width
Data Valid before WR Rising Edge
Data Hold after WR Rising Edge
Address Valid to WR Falling Edge
72 5
ns
55
ns
15
ns
17 5
ns
t_RDYS
t_RDYH
t_RDYV e WS a 0 25 t_C b 30
CHIP SELECT NATIVE BUS TIMING
RDY Falling Edge before CK2 Falling Edge
RDY Rising Edge after CK2 Falling Edge
RDY Falling Edge after RD or WR Falling Edge
45
ns
0
ns
32 5
ns
t_CS30RD e 0 75 t_C b 30
t_ACCS30 e t_C a WS b 30
t_CS21RD e 0 75 t_C b 35
t_ACCS21 e t_C a WS b 35
t_CSHR e t_C b 15
t_CS30WR e 0 75 t_C b 30
t_CS21WR e 0 75 t_C b 35
t_CSHW e 0 5 t_C b 15
CS3 CS0 Valid to RD Falling Edge
CS3 CS0 Valid to Input Data Valid
CS2 CS1 Valid to RD Falling Edge
CS2 CS1 Valid to Input Data Valid
Chip Select Hold after RD Rising Edge
CS3 CS0 Valid to WR Falling Edge
CS2 CS1 Valid to WR Falling Edge
Chip Select Hold after WR Rising Edge
75
ns
70
ns
25
ns
65
ns
35
ns
75
ns
25
ns
10
ns
4