HPC46100 Datasheet, PDF (26/32 Pages) National Semiconductor (TI) – HPC46100 High-Performance microController with DSP Capability

Shared Memory Support (Continued)
The host waits for the acknowledge signal (HLDA) from the
HPC46100 indicating that the system bus is free On receiv-
ing the acknowledge the host can rapidly transfer data into
or out of the shared memory by using a conventional DMA
controller Upon completion of the message transfer the
host removes the HOLD request and the HPC46100 re-
sumes normal operations
Memory
The HPC46100 has been designed to offer flexibility in
memory usage A total address space of 64 kbytes can be
directly addressed including 1024 bytes of RAM available
on the chip itself
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis Memory can be addressed
directly by instructions or indirectly through registers or any
memory word in the first 256 bytes of memory (On-Chip
Basepage RAM) Memory can be addressed as words or
bytes Words are always addressed on even-byte bounda-
ries The HPC46100 uses memory-mapped organization to
support registers I O and on-chip peripheral functions The
HPC46100 memory address space extends to 64 kbytes
and registers and I O are mapped as shown in Table III
TABLE III HPC46100 Memory Map
FFFF FFF0
FFEF FFD0
FFCF 0800
07FF 04C0
04BF 0196
0195 0194
0192
0191 0190
018F 018E
018D 018C
018B 018A
0189 0188
0187 0186
0185 0184
0183 0182
0181 0180
017F 0168
0167 0166
0165 0164
0163 0162
0161 0160
015F 0158
0157 0156
0155 0154
0153 0152
0151 0150
014F 012D
012C
012A
0128
0126
0124
0122
0120
011E
011C
011A
0118
0116
0114
0112
0110
010F 0109
Interrupt Vectors
JSRP Vectors
External Memory
On-Chip RAM
RESERVED
Watchdog Register
T0CON Register
TMMODE Register
DIVBY Register
T3 Timer
R3 Register
T2 Timer
R2 Register
I2CR Register R1
I3CR Register T1
I4CR Register
RESERVED
CSC3 Register
CSC2 Register
CSC1 Register
CSC0 Register
RESERVED
T6 Timer
T6CON Register
R6A Register
R6B Register
RESERVED
Baud Register
PSR Register
ENUR Register
TBUF Register
RBUF Register
ENUI Register
ENU Register
A D Result Register 7
A D Result Register 6
A D Result Register 5
A D Result Register 4
A D Result Register 3
A D Result Register 2
A D Result Register 1
A D Result Register 0
RESERVED
User
Memory
User
RAM
Watchdog
Logic
Timer
Block
T0 T3
Chip
Select
Control
Timer T6
UART
AD
Converter
0108
0106
0104
0102
0100
00FF 00FE
00FD 00FC
00FB 00FA
00F9 00F8
00F7 00F6
00F5 00F4
00F3 00F2
00F1 00F0
00EF 00EE
00ED 00EC
00EB 00EA
00E9 00E8
00E7 00E6
00E5 00E6
00E3 00E2
00E1 00E0
00DF 00DE
00DD 00DC
00DA
00D8
00D6
00D4
00D2
00D0
00CF 00CE
00CD 00CC
00CB 00CA
00C9 00C8
00C7 00C6
00C5 00C4
00C3 00C2
00C1 00C0
00BF 0000
EICON Register
ADCR3 Register
PORTD Register
ADCR2 Register
ADCR1 Register
T5 TIMER
T5CON Register
R5A Register
R5B Register
RESERVED
BFUN Register
DIR B Register
RESERVED
FOR DIRA
T4 TIMER
T4CON Register
R4A Register
R4B Register
RESERVED
FOR UPIC
RESERVED
PORTB Register
RESERVED
FOR PORTA
MRU (MRR upper)
MRL (MRR lower)
MIR
PORTI Register
SIO Register
IRCD Register
IRPD Register
ENIR Register
X Register
B Register
K Register
A Register
PC Register
SP Register
HALTEN Register
PSW Register
On-Chip RAM
EI Pin
Control
AD
Control
Timer 5
Ports
AB
Control
Timer 4
Ports A B
Math Unit
Interrupt
Control
Registers
HPC Core
Registers
Basepage
RAM
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